Loop aware IR-level annotation framework for performance estimation in native simulation. - Omayma Matoussi; Frédéric Pétrot (ASP-DAC, 2017)

IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress. - Omayma Matoussi; Frédéric Pétrot (CODES+ISSS, 2017)

Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation. - Omayma Matoussi; Frédéric Pétrot (DATE, 2017)

Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms. - Marcos Aurélio Pinto Cunha; Omayma Matoussi; Frédéric Pétrot (ACM Trans. Embed. Comput. Syst., 2017)

A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation. - Omayma Matoussi; Frédéric Pétrot (ASP-DAC, 2018)

Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation. - Omayma Matoussi; Frédéric Pétrot (Integr., 2019)