A framework for predictive dynamic temperature management of microprocessor systems. - Omer Khan; Sandip Kundu (ICCAD, 2008)

A self-adaptive system architecture to address transistor aging. - Omer Khan; Sandip Kundu (DATE, 2009)

Hardware/software co-design architecture for thermal management of chip multiprocessors. - Omer Khan; Sandip Kundu (DATE, 2009)

Improving yield and reliability of chip multiprocessors. - Abhisek Pan; Omer Khan; Sandip Kundu (DATE, 2009)

Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. - Omer Khan; Sandip Kundu (HiPEAC, 2009)

A model to exploit power-performance efficiency in superscalar processors via structure resizing. - Omer Khan; Sandip Kundu (ACM Great Lakes Symposium on VLSI, 2010)

A self-adaptive scheduler for asymmetric multi-cores. - Omer Khan; Sandip Kundu (ACM Great Lakes Symposium on VLSI, 2010)

Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. - Rance Rodrigues; Sandip Kundu; Omer Khan (ITC, 2010)

Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. - Omer Khan; Sandip Kundu (IEEE Trans. Computers, 2010)

Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. - Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu; Omer Khan (PACT, 2011)

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. - Omer Khan; Henry Hoffmann; Mieszko Lis; Farrukh Hijaz; Anant Agarwal; Srinivas Devadas (ICCD, 2011)

Scalable, accurate multicore simulation in the 1000-core era. - Mieszko Lis; Pengju Ren; Myong Hyon Cho; Keun Sup Shim; Christopher W. Fletcher; Omer Khan; Srinivas Devadas (ISPASS, 2011)

Deadlock-free fine-grained thread migration. - Myong Hyon Cho; Keun Sup Shim; Mieszko Lis; Omer Khan; Srinivas Devadas (NOCS, 2011)

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems. - Michel A. Kinsy; Omer Khan; Ivan Celanovic; Dusan Majstorovic; Nikola L. Celanovic; Srinivas Devadas (RTSS, 2011)

Brief announcement: distributed shared memory based on computation migration. - Mieszko Lis; Keun Sup Shim; Myong Hyon Cho; Christopher W. Fletcher; Michel A. Kinsy; Ilia A. Lebedev; Omer Khan; Srinivas Devadas (SPAA, 2011)

DCC: A Dependable Cache Coherence Multicore Architecture. - Omer Khan; Mieszko Lis; Yildiz Sinangil; Srinivas Devadas (IEEE Comput. Archit. Lett., 2011)

Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. - Omer Khan; Sandip Kundu (IEEE Trans. Dependable Secur. Comput., 2011)

Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. - Omer Khan; Sandip Kundu (Trans. High Perform. Embed. Archit. Compil., 2011)

A low-overhead dynamic optimization framework for multicores. - Christopher W. Fletcher; Rachael Harding; Omer Khan; Srinivas Devadas (PACT, 2012)

Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores. - Farrukh Hijaz; Qingchuan Shi; Omer Khan (MICRO Workshops, 2012)

Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. - Omer Khan; Sandip Kundu (IET Circuits Devices Syst., 2012)

HORNET: A Cycle-Level Multicore Simulator. - Pengju Ren; Mieszko Lis; Myong Hyon Cho; Keun Sup Shim; Christopher W. Fletcher; Omer Khan; Nanning Zheng 001; Srinivas Devadas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

MARTHA: architecture for control and emulation of power electronics and smart grid systems. - Michel A. Kinsy; Ivan Celanovic; Omer Khan; Srinivas Devadas (DATE, 2013)

A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages. - Farrukh Hijaz; Qingchuan Shi; Omer Khan (ICCD, 2013)

Towards efficient dynamic data placement in NoC-based multicores. - Qingchuan Shi; Farrukh Hijaz; Omer Khan (ICCD, 2013)

The locality-aware adaptive cache coherence protocol. - George Kurian; Omer Khan; Srinivas Devadas (ISCA, 2013)

A framework to accelerate sequential programs on homogeneous multicores. - Christopher W. Fletcher; Rachael Harding; Omer Khan; Srinivas Devadas (VLSI-SoC, 2013)

Toward Holistic Soft-Error-Resilient Shared-Memory Multicores. - Qingchuan Shi; Omer Khan (Computer, 2013)

Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. - Christopher W. Fletcher; Ling Ren 001; Xiangyao Yu; Marten van Dijk; Omer Khan; Srinivas Devadas (HPCA, 2014)

Locality-aware data replication in the Last-Level Cache. - George Kurian; Srinivas Devadas; Omer Khan (HPCA, 2014)

Thread Migration Prediction for Distributed Shared Caches. - Keun Sup Shim; Mieszko Lis; Omer Khan; Srinivas Devadas (IEEE Comput. Archit. Lett., 2014)

HaTCh: Hardware Trojan Catcher. - Syed Kamran Haider; Chenglu Jin; Masab Ahmad; Devu Manikantan Shila; Omer Khan; Marten van Dijk (IACR Cryptol. ePrint Arch., 2014)

NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages. - Farrukh Hijaz; Omer Khan (ACM Trans. Archit. Code Optim., 2014)

OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access. - George Kurian; Qingchuan Shi; Srinivas Devadas; Omer Khan (PACT, 2015)

Efficient parallelization of path planning workload on single-chip shared-memory multicores. - Masab Ahmad; Kartik Lakshminarasimhan; Omer Khan (HPEC, 2015)

CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores. - Masab Ahmad; Farrukh Hijaz; Qingchuan Shi; Omer Khan (IISWC, 2015)

Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads. - Masab Ahmad; Syed Kamran Haider; Farrukh Hijaz; Marten van Dijk; Omer Khan (HASP@ISCA, 2015)

Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication. - Farrukh Hijaz; Brian Kahne; Peter Wilson; Omer Khan (NAS, 2015)

A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads. - Qingchuan Shi; Henry Hoffmann; Omer Khan (IEEE Comput. Archit. Lett., 2015)

The Execution Migration Machine: Directoryless Shared-Memory Architecture. - Keun Sup Shim; Mieszko Lis; Omer Khan; Srinivas Devadas (Computer, 2015)

M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors. - Syed Kamran Haider; Masab Ahmad; Farrukh Hijaz; Astha Patni; Ethan Johnson; Matthew Seita; Omer Khan; Marten van Dijk (IACR Cryptol. ePrint Arch., 2015)

Foreword. - Omer Khan; Maria K. Michael; Antonio Miele; Qiaoyan Yu (DFT, 2016)

GPU concurrency choices in graph analytics. - Masab Ahmad; Omer Khan (IISWC, 2016)

Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. - Sandip Kundu; Omer Khan (VLSID, 2016)

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies. - Qingchuan Shi; George Kurian; Farrukh Hijaz; Srinivas Devadas; Omer Khan (ACM Trans. Archit. Code Optim., 2016)

Locality-aware data replication in the last-level cache for large scale multicores. - Farrukh Hijaz; Qingchuan Shi; George Kurian; Srinivas Devadas; Omer Khan (J. Supercomput., 2016)

GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms. - Hamza Omar; Masab Ahmad; Omer Khan (ICCD, 2017)

Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging. - Halit Dogan; Farrukh Hijaz; Masab Ahmad; Brian Kahne; Peter Wilson; Omer Khan (IPDPS, 2017)

Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads. - Qingchuan Shi; Hamza Omar; Omer Khan (CoRR, 2017)

Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs. - Masab Ahmad; Christopher J. Michael 001; Omer Khan (IEEE Micro, 2017)

Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72. - Halit Dogan; Masab Ahmad; José A. Joao; Omer Khan (ICCD, 2018)

Breaking the Oblivious-RAM Bandwidth Wall. - Hamza Omar; Syed Kamran Haider; Ling Ren 001; Marten van Dijk; Omer Khan (ICCD, 2018)

Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications. - Masab Ahmad; Halit Dogan; Fabio Checconi; Xinyu Que; Daniele Buono; Omer Khan (IPDPS, 2018)

Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications. - Hamza Omar; Halit Dogan; Brian Kahne; Omer Khan (IEEE Comput. Archit. Lett., 2018)

Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency. - Hamza Omar; Qingchuan Shi; Masab Ahmad; Halit Dogan; Omer Khan (ACM Trans. Embed. Comput. Syst., 2018)

Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology. - Maria K. Michael; Salvatore Pontarelli; Omer Khan (IEEE Trans. Emerg. Top. Comput., 2018)

POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms. - Masab Ahmad; Mohsin Shan; Akif Rehman; Omer Khan (PACT, 2019)

HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators. - Masab Ahmad; Halit Dogan; Christopher J. Michael 001; Omer Khan (ISPASS, 2019)

IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks. - Hamza Omar; Omer Khan (CoRR, 2019)

Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale. - Halit Dogan; Masab Ahmad; Brian Kahne; Omer Khan (ACM Trans. Archit. Code Optim., 2019)

Advancing the State-of-the-Art in Hardware Trojans Detection. - Syed Kamran Haider; Chenglu Jin; Masab Ahmad; Devu Manikantan Shila; Omer Khan; Marten van Dijk (IEEE Trans. Dependable Secur. Comput., 2019)

Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. - Ozgur Sinanoglu; Omer Khan (IEEE Trans. Emerg. Top. Comput., 2019)

IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications. - Hamza Omar; Omer Khan (HPCA, 2020)

Accelerating relax-ordered task-parallel workloads using multi-level dependency checking. - Masab Ahmad; Mohsin Shan; Akif Rehman; Omer Khan (ICS, 2020)

Exploring accelerator and parallel graph algorithmic choices for temporal graphs. - Akif Rehman; Masab Ahmad; Omer Khan (PMAM@PPoPP, 2020)

In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores. - Masab Ahmad; Halit Dogan; José A. Joao; Omer Khan (IEEE Micro, 2020)

OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks. - Hamza Omar; Brandon D'Agostino; Omer Khan (IEEE Trans. Computers, 2020)

ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor. - Usman Ali; Omer Khan (HOST, 2021)

An Efficient Algorithm for the Construction of Dynamically Updating Trajectory Networks. - Deniz Gurevin; Chris J. Michael 001; Omer Khan (HPEC, 2021)

Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems. - Salman Abdul Khaliq; Usman Ali; Omer Khan (HPEC, 2021)

Message from the General Chairs. - Omer Khan; Ravi Soundararajan (IISWC, 2021)

Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors. - Brandon D'Agostino; Omer Khan (SEED, 2021)

Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores. - Mohsin Shan; Omer Khan (IEEE Comput. Archit. Lett., 2021)

Autonomous Secure Remote Attestation even when all Used and to be Used Digital Keys Leak. - Marten van Dijk; Deniz Gurevin; Chenglu Jin; Omer Khan; Phuong Ha Nguyen (IACR Cryptol. ePrint Arch., 2021)

Bilinear Map Based One-Time Signature Scheme with Secret Key Exposure. - Marten van Dijk; Deniz Gurevin; Chenglu Jin; Omer Khan; Phuong Ha Nguyen (IACR Cryptol. ePrint Arch., 2021)

PRISM: Strong Hardware Isolation-based Soft-Error Resilient Multicore Architecture with High Performance and Availability at Low Hardware Overheads. - Hamza Omar; Omer Khan (ACM Trans. Archit. Code Optim., 2021)

HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores. - Mohsin Shan; Omer Khan (HPCA, 2022)

MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores. - Usman Ali; Omer Khan (ICCD, 2022)

Towards Real-Time Temporal Graph Learning. - Deniz Gurevin; Mohsin Shan; Tong Geng; Weiwen Jiang; Caiwen Ding; Omer Khan (ICCD, 2022)

On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond. - Zhirui Hu; Jinyang Li 001; Zhenyu Pan; Shanglin Zhou; Lei Yang 018; Caiwen Ding; Omer Khan; Tong Geng; Weiwen Jiang (ICCD, 2022)

CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM. - Yixuan Luo; Payman Behnam; Kiran Thorat; Zhuo Liu; Hongwu Peng; Shaoyi Huang; Shu Zhou; Omer Khan; Alexey Tumanov; Caiwen Ding; Tong Geng (ICCD, 2022)

Towards Sparsification of Graph Neural Networks. - Hongwu Peng; Deniz Gurevin; Shaoyi Huang; Tong Geng; Weiwen Jiang; Omer Khan; Caiwen Ding (ICCD, 2022)

Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware. - Usman Ali; Salman Abdul Khaliq; Omer Khan (ISQED, 2022)

Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores. - Usman Ali; Abdul Rasheed Sahni; Omer Khan (SEED, 2022)

SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors. - Jared Nye; Omer Khan (IEEE Comput. Archit. Lett., 2022)

A performance predictor for implementation selection of parallelized static and temporal graph algorithms. - Akif Rehman; Masab Ahmad; Omer Khan (Concurr. Comput. Pract. Exp., 2022)

Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks. - Xi Xie; Hongwu Peng; Amit Hasan 001; Shaoyi Huang; Jiahui Zhao; Haowen Fang; Wei Zhang; Tong Geng; Omer Khan; Caiwen Ding (ICCAD, 2023)

MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration. - Mohsin Shan; Deniz Gurevin; Jared Nye; Caiwen Ding; Omer Khan (ISPASS, 2023)

MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training. - Hongwu Peng; Xi Xie; Kaustubh Shivdikar; Md Amit Hasan 001; Jiahui Zhao; Shaoyi Huang; Omer Khan; David R. Kaeli; Caiwen Ding (CoRR, 2023)

Hardware Root-of-Trust implementations in Trusted Execution Environments. - Usman Ali; Hamza Omar; Chujiao Ma; Vaibhav Garg; Omer Khan (IACR Cryptol. ePrint Arch., 2023)

Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware. - Usman Ali; Sheikh Abdul Rasheed Sahni; Omer Khan (ACM J. Emerg. Technol. Comput. Syst., 2023)

ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes. - Abdul Rasheed Sahni; Hamza Omar; Usman Ali; Omer Khan (ACM Trans. Archit. Code Optim., 2023)

MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training. - Hongwu Peng; Xi Xie; Kaustubh Shivdikar; Md Amit Hasan 001; Jiahui Zhao; Shaoyi Huang; Omer Khan; David R. Kaeli; Caiwen Ding (ASPLOS (2), 2024)

Masked Memory Primitive for Key Insulated Schemes. - Zachary DiMeglio; Jenna Bustami; Deniz Gurevin; Chenglu Jin; Marten van Dijk; Omer Khan (HOST, 2024)

PruneGNN: Algorithm-Architecture Pruning Framework for Graph Neural Network Acceleration. - Deniz Gurevin; Mohsin Shan; Shaoyi Huang; Md Amit Hasan 001; Caiwen Ding; Omer Khan (HPCA, 2024)

SSE: Security Service Engines to Scale Enclave Parallelism for System Interactive Applications. - Jared Nye; Usman Ali; Omer Khan (SEED, 2024)

Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency. - Deniz Gurevin; Caiwen Ding; Omer Khan (IEEE Comput. Archit. Lett., 2024)

OPMOS: Ordered Parallel Multi-Objective Shortest-Path. - Leo Gold; Adam Bienkowski; David Sidoti; Krishna R. Pattipati; Omer Khan (CoRR, 2024)

ASPLOS 2024 Artifact for "MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training". - Hongwu Peng; Xi Xie; Kaustubh Shivdikar; Amit Hasan 001; Jiahui Zhao; Shaoyi Huang; Omer Khan; David R. Kaeli; Caiwen Ding (Zenodo, 2024)

ASPLOS 2024 Artifact for "MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training". - Hongwu Peng; Xi Xie; Kaustubh Shivdikar; Amit Hasan 001; Jiahui Zhao; Shaoyi Huang; Omer Khan; David R. Kaeli; Caiwen Ding (Zenodo, 2024)

Graph Input-Aware Matrix Multiplication for Pruned Graph Neural Network Acceleration. - Hanan Khan; Deniz Gurevin; Omer Khan (IPDPS, 2025)

A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks. - Omer Khan (IEEE Comput. Archit. Lett., 2025)

Secure Remote Attestation With Strong Key Insulation Guarantees. - Deniz Gurevin; Chenglu Jin; Phuong Ha Nguyen; Omer Khan; Marten van Dijk (IEEE Trans. Computers, 2025)