FPGA Prototyping and Accelerated Verification of ASIPs. - Jakub Podivinsky; Marcela Simková; Ondrej Cekan; Zdenek Kotásek (DDECS, 2015)

Software Fault Tolerance: The Evaluation by Functional Verification. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (DSD, 2015)

The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. - Jakub Podivinsky; Ondrej Cekan; Marcela Simková; Zdenek Kotásek (Microprocess. Microsystems, 2015)

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Zdenek Kotásek (DSD, 2016)

Random stimuli generation based on a stochastic context-free grammar. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (FPT, 2016)

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Zdenek Kotásek (FPT, 2016)

A Probabilistic Context-Free Grammar Based Random Test Program Generation. - Ondrej Cekan; Zdenek Kotásek (DSD, 2017)

Reliability Analysis and Improvement of FPGA-Based Robot Controller. - Jakub Podivinsky; Jakub Lojda; Ondrej Cekan; Richard Panek; Zdenek Kotásek (DSD, 2017)

Functional verification based platform for evaluating fault tolerance properties. - Jakub Podivinsky; Ondrej Cekan; Jakub Lojda; Marcela Zachariásová; Martin Krcma; Zdenek Kotásek (Microprocess. Microsystems, 2017)

Program Generation Through a Probabilistic Constrained Grammar. - Ondrej Cekan; Jakub Podivinsky; Zdenek Kotásek (DSD, 2018)

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. - Jakub Lojda; Jakub Podivinsky; Ondrej Cekan; Richard Panek; Zdenek Kotásek (DSD, 2018)

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. - Jakub Podivinsky; Jakub Lojda; Ondrej Cekan; Zdenek Kotásek (DSD, 2018)

Input and Output Generation for the Verification of ALU: A Use Case. - Ondrej Cekan; Richard Panek; Zdenek Kotásek (EWDTS, 2018)

A Processor Optimization Framework for a Selected Application. - Jalab Podivinsky; Ondrej Cekan; Martin Krcma; Radek Burget; Tomas Hruska; Zdenek Kotásek (EWDTS, 2018)

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. - Ondrej Cekan; Jakub Podivinsky; Jakub Lojda; Richard Panek; Martin Krcma; Zdenek Kotásek (DSD, 2019)

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. - Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Radek Burget; Tomas Hruska; Zdenek Kotásek (DSD, 2019)

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. - Jakub Lojda; Jakub Podivinsky; Ondrej Cekan; Richard Panek; Martin Krcma; Zdenek Kotásek (DDECS, 2020)

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (DSD, 2020)

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (EWDTS, 2020)

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. - Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Radek Burget; Tomas Hruska; Zdenek Kotásek (LASCAS, 2020)

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. - Jakub Podivinsky; Jakub Lojda; Richard Panek; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (LASCAS, 2020)

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. - Jakub Lojda; Richard Panek; Jakub Podivinsky; Ondrej Cekan; Martin Krcma; Zdenek Kotásek (LATS, 2021)

Principy generování testovacích stimulů ; Principles of test stimuli generation. - Ondrej Cekan (2024)