A versatile structure of S31-GGA-casc switched-current memory cell with complex suppression of memorizing errors. - Ondrej Subrt (ESSCIRC, 2003)

A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters. - Ondrej Subrt; Pravoslav Martínek (DDECS, 2006)

Developing Virtual ADC Testing Environment in MAPLE. - Petr Struhovský; Ondrej Subrt; Jirí Hospodka; Pravoslav Martínek (DDECS, 2007)

Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform. - Ondrej Subrt; Petr Struhovský; Pravoslav Martínek; Jirí Hospodka (DDECS, 2008)

Experience in Virtual Testing of RSD cyclic A/D converters. - Miloslav Kubar; Ondrej Subrt; Pravoslav Martínek; Jiri Jakovenko (DDECS, 2009)

Versatile sub-bandgap reference IP core. - Tomás Urban; Ondrej Subrt; Pravoslav Martínek (DDECS, 2010)

The Algorithmizable Modeling of the Object-Oriented Data Model in Craft.CASE. - Ondrej Subrt; Vojtech Merunka (EOMAS@CAiSE, 2016)

SC Filter Optimization Performance by Hybrid Simplex Algorithm. - Jiri Nahlik; Jirí Hospodka; Ondrej Subrt (SMACD, 2018)

Modified Differential Evolution in the Load Balancing Problem for the iFDAQ of the COMPASS Experiment at CERN. - Ondrej Subrt; Martin Bodlák; Matous Jandek; Vladimír Jarý; Antonín Kveton; Josef Nový; Jan Tomsa; Miroslav Virius (IJCCI, 2019)

Reinforcement Learning in the Load Balancing Problem for the iFDAQ of the COMPASS Experiment at CERN. - Ondrej Subrt; Martin Bodlák; Matous Jandek; Vladimír Jarý; Antonín Kveton; Josef Nový; Miroslav Virius; Martin Zemko (ICAART (2), 2020)

Dynamic Programming and Greedy Heuristic in the Load Balancing Problem for the iFDAQ of the COMPASS Experiment at CERN. - Ondrej Subrt; Martin Bodlák; Vladimír Jarý; Antonín Kveton; Josef Nový; Miroslav Virius; Martin Zemko (ISEEIE, 2021)