A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching. - Chan-Hong Park; Ook Kim; Beomsup Kim (IEEE J. Solid State Circuits, 2001)

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm. - Hyung-Rok Lee; Ook Kim; Keewook Jung; John Shin; Deog-Kyoon Jeong (ISSCC, 2006)

A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. - Hyochang Kim; Jaewoo Park; Woosang Han; Kyuhwan Oh; Taekjun Ahn; Jun-Gi Jo; Ook Kim; Changsik Yoo (ICCE, 2016)

Duty-cycle and phase spacing error correction circuit for high-speed serial link. - Hyochang Kim; Ook Kim; Changsik Yoo (IEICE Electron. Express, 2017)

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. - Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)