Petri Net Analysis Using Boolean Manipulation. - Enric Pastor; Oriol Roig; Jordi Cortadella; Rosa M. Badia (Application and Theory of Petri Nets, 1994)

A generalized vision of some parallel bidiagonal systems solvers. - Josep Lluís Larriba-Pey; Juan J. Navarro; Oriol Roig; Angel Jorba (International Conference on Supercomputing, 1994)

Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets. - Oriol Roig; Jordi Cortadella; Enric Pastor (Application and Theory of Petri Nets, 1995)

Hierarchical gate-level verification of speed-independent circuits. - Oriol Roig; Jordi Cortadella; Enric Pastor (ASYNC, 1995)

Checking signal transition graph implementability by symbolic BDD traversal. - Alex Kondratyev; Jordi Cortadella; Michael Kishinevsky; Enric Pastor; Oriol Roig; Alexandre Yakovlev (ED&TC, 1995)

A new look at the conditions for the synthesis of speed-independent circuits. - Enric Pastor; Jordi Cortadella; Oriol Roig (Great Lakes Symposium on VLSI, 1995)

Review of General and Toeplitz Vector Bidiagonal Solvers. - Josep Lluís Larriba-Pey; Juan J. Navarro; Angel Jorba; Oriol Roig (Parallel Comput., 1996)

Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. - Oriol Roig; Jordi Cortadella; Marco A. Peña; Enric Pastor (DAC, 1997)

Structural methods for the synthesis of speed-independent circuits. - Enric Pastor; Jordi Cortadella; Alex Kondratyev; Oriol Roig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Symbolic Analysis of Bounded Petri Nets. - Enric Pastor; Jordi Cortadella; Oriol Roig (IEEE Trans. Computers, 2001)

Checking Delay-Insensitivity: 104 Gates and Beyond. - Alex Kondratyev; Oriol Roig; Lawrence Neukom; Karl Fant; Alexander Taubin (ASYNC, 2002)