Synthesis of passive filter using object oriented genetic algorithm. - Orlando Verducci Jr.; Paulo César Crepaldi; Leonardo Breseghello Zoccal; Tales C. Pimenta (ICM, 2014)

Software-Defined Radio design based on GALS architecture for FPGAs. - Eduardo Lussari; Duarte Lopes de Oliveira; Lester de Abreu Faria; Orlando Verducci Jr. (SBCCI, 2016)

An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines. - Duarte Lopes de Oliveira; Orlando Verducci Jr.; Vitor L. V. Torres; Gracieth Cavalcanti Batista; Robson L. Moreno; Leonardo Romano (LASCAS, 2019)

Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. - Diego A. Silva; Orlando Verducci Jr.; Duarte Lopes de Oliveira (VLSI-SoC, 2019)

Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Robson L. Moreno (LATS, 2021)

A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista; Tiago S. Curtinhas (Microelectron. J., 2021)

Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. - Orlando Verducci Jr.; Duarte Lopes de Oliveira; Gracieth Cavalcanti Batista (LASCAS, 2022)