A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. - Ryu Ogiwara; Sumio Tanaka; Yasuo Itoh; Tadashi Miyakawa; Yoshiaki Takeuchi; Sumiko Mano Doumae; Hiroyuki Takenaka; Iwao Kunishima; Susumu Shuto; Osamu Hidaka; Sumito Ohtsuki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 2000)