Design of a second-level cache chip for shared-bus multimicroprocessor systems. - Kunio Uchiyama; Hirokazu Aoki; Osamu Nishii; Susumu Hatano; Osamu Nagashima; Kanji Oishi; Jun Kitano (IEEE J. Solid State Circuits, 1991)

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. - Hiroki Fujisawa; Takeshi Sakata; Tomonori Sekiguchi; Osamu Nagashima; Katsutaka Kimura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 1997)