Design of a second-level cache chip for shared-bus multimicroprocessor systems. - Kunio Uchiyama; Hirokazu Aoki; Osamu Nishii; Susumu Hatano; Osamu Nagashima; Kanji Oishi; Jun Kitano (IEEE J. Solid State Circuits, 1991)

A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems. - Tetsuhiko Okada; Susumu Narita; Osamu Nishii; Noriharu Hiratsuka; Nobuyuki Hayashi; Mitsuo Asai; Shinji Fujiwara; Mikiko Satoh; Junichi Nishimoto; Hirokazu Aoki; Kunio Uchiyama; Shigeru Matsuo; et al. (COMPCON, 1994)

SH4 RISC multimedia microprocessor. - Fumio Arakawa; Osamu Nishii; Kunio Uchiyama; Norio Nakagawa (IEEE Micro, 1998)

Low-Power Design of 90-nm SuperH Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (ICCD, 2005)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

SH-X: an embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Motokazu Ozawa; Osamu Nishii; Toshihiro Hattori (SIGARCH Comput. Archit. News, 2005)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (IEICE Trans. Electron., 2006)

SH-X: An embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Osamu Nishii; Toshihiro Hattori (J. Embed. Comput., 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU. - Fumio Arakawa; Takashi Okada; Tomoichi Hayashi; Osamu Nishii; Toshihiro Hattori (Microprocess. Microsystems, 2009)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

Low Power Platform for Embedded Processor LSIs. - Toru Shimizu; Kazutami Arimoto; Osamu Nishii; Sugako Otani; Hiroyuki Kondo (IEICE Trans. Electron., 2011)