A Hierarchical Standard Cell Approach for Custom VLSI Design. - Takeshi Tokuda; Jiro Korematsu; Osamu Tomisawa; Sotoju Asai; Isao Ohkura; Tatsuya Enomoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

A macrocell approach for VLSI processor design. - Takeshi Tokuda; Jiro Korematsu; Yukihiko Shimazu; Narumi Sakashita; Tohru Kengaku; Toshiki Fugiyama; Takio Ohno; Osamu Tomisawa (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

An elastic pipeline mechanism by self-timed circuits. - Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Katsuhiko Asada; Hiroaki Terada (IEEE J. Solid State Circuits, 1988)

VLSI implementation of a variable-length pipeline scheme for data-driven processors. - Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. - Shinji Komori; Hidehiro Takata; Todhixuki Tamura; Fumixsdu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

M32R/D-integrating DRAM and microprocessor. - Yasuhiro Nunomura; Toru Shimizu; Osamu Tomisawa (IEEE Micro, 1997)