A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. - Tomoaki Yabe; Shinji Miyano; Katsuhiko Sato; Masaharu Wada; Ryo Haga; Osamu Wada; Motohiro Enkaku; Takehiko Hojyo; Kenichiro Mimoto; Masaaki Tazawa; Tsutomu Ohkubo; Kenji Numata (IEEE J. Solid State Circuits, 1998)

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. - Toshimasa Namekawa; Shinji Miyano; Ryo Fukuda; Ryo Haga; Osamu Wada; Hironori Banba; Satoru Takeda; Kazuhiro Suda; Kenichiro Mimoto; Satoshi Yamaguchi; Tsutomu Ohkubo; Hiroshi Takato; et al. (IEEE J. Solid State Circuits, 2000)

Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. - Osamu Wada; Toshimasa Namekawa; Hiroshi Ito; Atsushi Nakayama; Shuso Fujii (ITC, 2004)

1/2fs Direct RF Under Sampling Receiver for Multi Channel Satellite Systems. - Daliso Banda; Mizuki Motoyoshi; Tomokazu Koizumi; Osamu Wada; Tuan Thanh Ta; Suguru Kameda; Noriharu Suematsu; Tadashi Takagi; Kazuo Tsubouchi (IEICE Trans. Electron., 2015)