Reusing cached schedules in an out-of-order processor with in-order issue logic. - Oscar Palomar; Toni Juan; Juan J. Navarro (ICCD, 2009)

Reusing cached schedules in an out-of-order processor with in-order issue logic. - Oscar Palomar (2011)

Vector Extensions for Decision Support DBMS Acceleration. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (MICRO, 2012)

On the selection of adder unit in energy efficient vector processing. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISQED, 2013)

ReCompAc: Reconfigurable compute accelerator. - Milovan Duric; Oscar Palomar; Aaron Smith (ReConFig, 2013)

Stand-Alone Memory Controller for Graphics System. - Tassadaq Hussain; Oscar Palomar; Osman S. Ünsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Amna Haider (ARC, 2014)

PVMC: Programmable Vector Memory Controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (ASAP, 2014)

VALib and SimpleVector: tools for rapid initial research on vector architectures. - Milan Stanic; Oscar Palomar; Ivan Ratkovic; Milovan Duric; Osman S. Unsal; Adrián Cristal (Conf. Computing Frontiers, 2014)

EVX: Vector execution on low power EDGE cores. - Milovan Duric; Oscar Palomar; Aaron Smith; Osman S. Unsal; Adrián Cristal; Mateo Valero; Doug Burger (DATE, 2014)

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy. - Santhosh Kumar Rethinagiri; Oscar Palomar; Anita Sobe; Thomas Knauth; Wojciech M. Barczynski; Gulay Yalcin; Yarco Hayduk; Adrián Cristal; Osman S. Unsal; Pascal Felber; Christof Fetzer; Julien Ryckaert; et al. (DSD, 2014)

System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Gulay Yalcin; Osman S. Unsal; Adrián Cristal (ESTIMedia, 2014)

APMC: advanced pattern based memory controller (abstract only). - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Santhosh Kumar Rethinagiri (FPGA, 2014)

Power estimation tool for system on programmable chip based platforms (abstract only). - Santhosh Kumar Rethinagiri; Oscar Palomar; Adrián Cristal; Osman S. Unsal (FPGA, 2014)

MAPC: Memory access pattern based controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (FPL, 2014)

AMMC: Advanced Multi-Core Memory Controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Shakaib A. Gursal (FPT, 2014)

Advanced Pattern based Memory Controller for FPGA based HPC applications. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (HPCS, 2014)

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. - Milan Stanic; Oscar Palomar; Ivan Ratkovic; Milovan Duric; Osman S. Unsal; Adrián Cristal; Mateo Valero (HPCS, 2014)

PETS: Power and energy estimation tool at system-level. - Santhosh Kumar Rethinagiri; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Rabie Ben Atitallah; Smaïl Niar (ISQED, 2014)

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISVLSI, 2014)

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal; Morteza Biglari-Abhari (ISVLSI, 2014)

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal (PATMOS, 2014)

System-level power estimation tool for embedded processor based platforms. - Santhosh Kumar Rethinagiri; Oscar Palomar; Rabie Ben Atitallah; Smaïl Niar; Osman S. Unsal; Adrián Cristal Kestelman (RAPIDO, 2014)

PAMS: Pattern Aware Memory System for embedded systems. - Tassadaq Hussain; Nehir Sönmez; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Shakaib A. Gursal (ReConFig, 2014)

Dynamic-vector execution on a general purpose EDGE chip multiprocessor. - Milovan Duric; Oscar Palomar; Aaron Smith; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero; Doug Burger; Alexander V. Veidenbaum (ICSAMOS, 2014)

DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level. - Santhosh Kumar Rethinagiri; Oscar Palomar; Adrián Cristal; Osman S. Unsal; Michael M. Swift (SoCC, 2014)

ViPS: Visual processing system for medical imaging. - Tassadaq Hussain; Oscar Palomar; Adrián Cristal; Eduard Ayguadé; Amna Haider (BMEI, 2015)

An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal (COOL Chips, 2015)

Runtime-Aware Architectures. - Marc Casas; Miquel Moretó; Lluc Alvarez; Emilio Castillo; Dimitrios Chasapis; Timothy Hayes 001; Luc Jaulmes; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Jesús Labarta; et al. (Euro-Par, 2015)

Heterogeneous Platform to Accelerate Compute Intensive Applications. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal (FCCM, 2015)

Trigeneous Platforms for Energy Efficient Computing of HPC Applications. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal (HiPC, 2015)

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (HPCA, 2015)

VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Osman S. Unsal; Adrián Cristal (ICCD, 2015)

DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores. - J. Rubén Titos Gil; Oscar Palomar; Osman S. Unsal; Adrián Cristal (ICPP, 2015)

Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Milovan Duric; Djordje Peic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISVLSI, 2015)

Imposing coarse-grained reconfiguration to general purpose processors. - Milovan Duric; Milan Stanic; Ivan Ratkovic; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero; Aaron Smith (SAMOS, 2015)

FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level. - Santhosh Kumar Rethinagiri; Oscar Palomar; Javier Arias Moreno; Adrián Cristal; Osman S. Unsal (SoCC, 2015)

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers. - Santhosh Kumar Rethinagiri; Oscar Palomar; Anita Sobe; Gulay Yalcin; Thomas Knauth; J. Rubén Titos Gil; Pablo Prieto; Malte Schneegaß; Adrián Cristal; Osman S. Unsal; Pascal Felber; Christof Fetzer; et al. (Microprocess. Microsystems, 2015)

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. - Milan Stanic; Oscar Palomar; Timothy Hayes 001; Ivan Ratkovic; Osman S. Unsal; Adrián Cristal; Mateo Valero (PACT, 2016)

Towards low-power embedded vector processor. - Milan Stanic; Oscar Palomar; Timothy Hayes 001; Ivan Ratkovic; Osman S. Unsal; Adrián Cristal (Conf. Computing Frontiers, 2016)

Energy minimization at all layers of the data center: The ParaDIME project. - Oscar Palomar; Santhosh Kumar Rethinagiri; Gulay Yalcin; J. Rubén Titos Gil; Pablo Prieto; Emma Torrella; Osman S. Unsal; Adrián Cristal; Pascal Felber; Anita Sobe; Yaroslav Hayduk; Mascha Kurpicz; et al. (DATE, 2016)

Future Vector Microprocessor Extensions for Data Aggregations. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISCA, 2016)

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISLPED, 2016)

Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm. - Gulay Yalcin; Santhosh Kumar Rethinagiri; Oscar Palomar; Osman S. Ünsal; Adrián Cristal; Dragomir Milojevic (PDP, 2016)

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. - Oriol Arcas-Abella; Adrià Armejach; Timothy Hayes 001; Gorker Alp Malazgirt; Oscar Palomar; Behzad Salami 001; Nehir Sönmez (Comput. Sci. Eng., 2016)

Architectural support for efficient message passing on shared memory multi-cores. - J. Rubén Titos Gil; Oscar Palomar; Osman S. Unsal; Adrián Cristal (J. Parallel Distributed Comput., 2016)

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation. - John Mawer; Oscar Palomar; Cosmin Gorgovan; Andy Nisbet; Will Toms; Mikel Luján (FCCM, 2017)

An Integrated Vector-Scalar Design on an In-Order ARM Core. - Milan Stanic; Oscar Palomar; Timothy Hayes 001; Ivan Ratkovic; Adrián Cristal; Osman S. Unsal; Mateo Valero (ACM Trans. Archit. Code Optim., 2017)

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality. - Sajad Saeedi 001; Bruno Bodin; Harry Wagstaff; Andy Nisbet; Luigi Nardi; John Mawer; Nicolas Melot; Oscar Palomar; Emanuele Vespa; Tom Spink; Cosmin Gorgovan; Andrew M. Webb; et al. (CoRR, 2018)

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality. - Sajad Saeedi 001; Bruno Bodin; Harry Wagstaff; Andy Nisbet; Luigi Nardi; John Mawer; Nicolas Melot; Oscar Palomar; Emanuele Vespa; Tom Spink; Cosmin Gorgovan; Andrew M. Webb; et al. (Proc. IEEE, 2018)

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman Sabri Unsal; Adrián Cristal; Mateo Valero (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Memory Controller for Vector Processor. - Tassadaq Hussain; Oscar Palomar; Osman S. Ünsal; Adrián Cristal; Eduard Ayguadé (J. Signal Process. Syst., 2018)

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs. - Konstantinos Iordanou; Oscar Palomar; John Mawer; Cosmin Gorgovan; Andy Nisbet; Mikel Luján (FCCM, 2019)

Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020). - Miquel Pericàs; Oscar Palomar; Vassilis Papaefstathiou; Mahmoud Eljammaly (CoRR, 2020)

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. - Cristóbal Ramírez; César-Alejandro Hernández-Calderón; Oscar Palomar; Osman S. Unsal; Marco Antonio Ramírez; Adrián Cristal (ACM Trans. Archit. Code Optim., 2020)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. - Lluc Alvarez; Abraham Ruiz; Arnau Bigas-Soldevilla; Pavel Kuroedov; Alberto González 004; Hamsika Mahale; Noe Bustamante; Albert Aguilera; Francesco Minervini; Javier Salamero; Oscar Palomar; Vassilis Papaefstathiou; et al. (CF, 2023)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit. - Mate Kovac; Leon Dragic; Branimir Malnar; Francesco Minervini; Oscar Palomar; Carlos Rojas; Mauro Olivieri; Josip Knezovic; Mario Kovac (Microprocess. Microsystems, 2023)

Functional Verification of a RISC-V Vector Accelerator. - Víctor Jiménez; Mario Rodríguez; Marc Domínguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sönmez; Oscar Palomar; Miquel Moretó (IEEE Des. Test, 2023)

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. - Francesco Minervini; Oscar Palomar; Osman S. Unsal; Enrico Reggiani; Josue V. Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto González 004; Jonnatan Mendoza; Iván Vargas; et al. (ACM Trans. Archit. Code Optim., 2023)