An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. - Oscar Ruano; Pilar Reyes; Juan Antonio Maestro; Luca Sterpone; Pedro Reviriego (DDECS, 2007)

Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. - Pilar Reyes; Pedro Reviriego; Juan Antonio Maestro; Oscar Ruano (J. Signal Process. Syst., 2008)

Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. - Juan Antonio Maestro; Pedro Reviriego; Pilar Reyes; Oscar Ruano (Integr., 2009)

Validation and optimization of TMR protections for circuits in radiation environments. - Oscar Ruano; Juan Antonio Maestro; Pedro Reviriego (DDECS, 2011)

A fast and efficient technique to apply Selective TMR through optimization. - Oscar Ruano; Juan Antonio Maestro; Pedro Reviriego (Microelectron. Reliab., 2011)

Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. - Pedro Reviriego; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. - Pedro Reviriego; Oscar Ruano; Mark F. Flanagan; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Access, 2021)

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. - Oscar Ruano; Francisco Garcia-Herrero; Luis Alberto Aranda; Alfonso Sánchez-Macián; Laura Rodriguez; Juan Antonio Maestro (Sensors, 2021)

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (Comput. Electr. Eng., 2022)

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. - Luis Alberto Aranda; Oscar Ruano; Francisco Garcia-Herrero; Juan Antonio Maestro (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. - Jefferson Andres Bravo-Montes; Alonso Martín-Toledano; Alfonso Sánchez-Macián; Oscar Ruano; Francisco Garcia-Herrero (J. Supercomput., 2022)

RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. - Yao-Ming Kuo; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Computers, 2023)

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. - Yao-Ming Kuo; Mark F. Flanagan; Francisco Garcia-Herrero; Oscar Ruano; Juan Antonio Maestro (IEEE Trans. Aerosp. Electron. Syst., 2023)

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. - José Luis Imaña; Luis Piñuel; Yao-Ming Kuo; Oscar Ruano; Francisco Garcia-Herrero (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications. - Daniel Báscones; Francisco Garcia-Herrero; Oscar Ruano; Carlos González 002; Daniel Mozos; Juan Antonio Maestro (IEEE Trans. Computers, 2025)