Synthesis strategies for sub-VT systems. - Pascal Andreas Meinerzhagen; Oskar Andersson; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ECCTD, 2011)

Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. - Oskar Andersson; S. M. Yasser Sherazi; Joachim Neves Rodrigues (NORCHIP, 2011)

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. - Pascal Andreas Meinerzhagen; Oskar Andersson; Babak Mohammadi; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ESSCIRC, 2012)

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC, 2012)

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. - Jeremy Constantin; Ahmed Yasir Dogan; Oskar Andersson; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues; David Atienza; Andreas Burg 001 (VLSI-SoC (Selected Papers), 2012)

Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg 001; Joachim Neves Rodrigues (ESSCIRC, 2013)

A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. - Christoph Thomas Muller; Steffen Malkowsky; Oskar Andersson; Babak Mohammadi; Jens Sparsø; Joachim Neves Rodrigues (VLSI-SoC, 2013)

A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Andreas Meinerzhagen; Joachim Neves Rodrigues (ESSCIRC, 2014)

A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS. - Oskar Andersson; Joachim Neves Rodrigues (ISCAS, 2015)

Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication. - Farhana Sheikh; Oskar Andersson; Ching-En Lee; Feng Xue; Chia-Hsiang Chen; Anuja Vaidya; Ankit Sharma; Tom Tetzlaff (SiPS, 2015)

A 290 mV Sub-V𝕋 ASIC for Real-Time Atrial Fibrillation Detection. - Oskar Andersson; Ki H. Chon; Leif Sörnmo; Joachim Neves Rodrigues (IEEE Trans. Biomed. Circuits Syst., 2015)

An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Xiao Luo; Masoud Nouripayam; Joachim Neves Rodrigues (A-SSCC, 2016)

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (ESSCIRC, 2016)

Logic filter cache for wide-VDD-range processors. - Alen Bardizbanyan; Oskar Andersson; Joachim Neves Rodrigues; Per Larsson-Edefors (ICECS, 2016)

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS. - Nafiseh Seyed Mazloum; Joachim Neves Rodrigues; Oskar Andersson; Anders Nejdel; Ove Edfors (CoRR, 2016)

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. - Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg 001; Joachim Neves Rodrigues (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Adaptive and multi-mode baseband systems for next generation wireless communication. - Farhana Sheikh; Ankit Sharma; Oskar Andersson; Mehnaz Rahman; Dongmin Yoon; Alexios Balatsoukas-Stimming; Deepak Dasalukunte; Anthony Chun (ACSSC, 2017)

65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography. - Shahzad Asif; Oskar Andersson; Joachim Neves Rodrigues; Yinan Kong (IET Comput. Digit. Tech., 2018)

A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI. - Babak Mohammadi; Oskar Andersson; Joseph Nguyen; Lorenzo Ciampolini; Andreia Cathelin; Joachim Neves Rodrigues (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Neural Network Engine for Resource Constrained Embedded Systems. - Zuzana Jelcicová; Adrian Mardari; Oskar Andersson; Evangelia Kasapaki; Jens Sparsø (ACSSC, 2020)

A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. - Zuzana Jelcicová; Evangelia Kasapaki; Oskar Andersson; Jens Sparsø (ISCAS, 2023)

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. - Zuzana Jelcicová; Evangelia Kasapaki; Oskar Andersson; Jens Sparsø (IEEE Trans. Very Large Scale Integr. Syst., 2024)