An effective buffer planning algorithm for IP based fixed-outline SOC placement. - Ou He; Sheqin Dong; Jinian Bian; Yuchun Ma; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2007)

Symmetry constraint based on mismatch analysis for analog layout in SOI technology. - Jiayi Liu; Sheqin Dong; Xianlong Hong; Yibo Wang 009; Ou He; Satoshi Goto (ASP-DAC, 2008)

A novel fixed-outline floorplanner with zero deadspace for hierarchical design. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ICCAD, 2008)

Bus via reduction based on floorplan revising. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ACM Great Lakes Symposium on VLSI, 2010)

Chemical-mechanical polishing aware application-specific 3D NoC design. - Wooyoung Jang; Ou He; Jae-Seok Yang; David Z. Pan (ICCAD, 2011)

Novel and efficient min cut based voltage assignment in gate level. - Tao Lin; Sheqin Dong; Song Chen 001; Yuchun Ma; Ou He; Satoshi Goto (ISQED, 2011)

Buffer Planning for IP Placement Using Sliced-LFF. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto (VLSI Design, 2011)

UNISM: Unified Scheduling and Mapping for General Networks on Chip. - Ou He; Sheqin Dong; Wooyoung Jang; Jinian Bian; David Z. Pan (IEEE Trans. Very Large Scale Integr. Syst., 2012)