A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation. - Bjørnar Hernes; Øystein Moldsvor; Trond Sæther (ISCAS (1), 2001)

A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. - Terje N. Andersen; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Bjørnar Hernes; Øystein Moldsvor (DATE, 2004)

A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS. - Terje N. Andersen; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Bjørnar Hernes; Øystein Moldsvor (ESSCIRC, 2004)

A 220mW 14b 40MSPS gain calibrated pipelined ADC. - Johnny Bjørnsen; Øystein Moldsvor; Trond Sæther; Trond Ytterdal (ESSCIRC, 2005)

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS. - Terje Nortvedt Andersen; Bjørnar Hernes; Atle Briskemyr; Frode Telstø; Johnny Bjørnsen; Thomas E. Bonnerud; Øystein Moldsvor (IEEE J. Solid State Circuits, 2005)

A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS. - Bjørnar Hernes; Johnny Bjørnsen; Terje N. Andersen; Anders Vinje; Havard Korsvoll; Frode Telstø; Atle Briskemyr; Christian Holdo; Øystein Moldsvor (ISSCC, 2007)