A 12 bit, 2-MS/s, 0.016-mm2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator. - Saikrishna Ganta; Alfredo Tomasini; Ajay Taparia; Taehee Cho; Mandar Kulkarni; Ozan Erdogan (ESSCIRC, 2016)