Ozcan Ozturk

According to our database1, Ozcan Ozturk authored at least 118 papers between 2004 and 2018.

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Bibliography

2018
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance.
Embedded Systems Letters, 2018

2017
Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures.
IEEE Trans. Computers, 2017

Graph Analytics Accelerators for Cognitive Systems.
IEEE Micro, 2017

Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

Message from the general chair.
Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Reconfigurable Hardened Latch and Flip-Flop for FPGAs.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Pipelined fission for stream programs with dynamic selectivity and partitioned state.
J. Parallel Distrib. Comput., 2016

Implications of non-volatile memory as primary storage for database management systems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Energy Efficient Architecture for Graph Analytics Accelerators.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Keynote 1: "Analysis of design parameters in safety-critical systems".
Proceedings of the 11th International Design & Test Symposium, 2016

Adaptive routing framework for network on chip architectures.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

FPGA implementation of a fault-tolerant application-specific NoC design.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Register file reliability enhancement through adjacent narrow-width exploitation.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Boosting performance of directory-based cache coherence protocols with coherence bypass at subpage granularity and a novel on-chip page table.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Application mapping algorithms for mesh-based network-on-chip architectures.
The Journal of Supercomputing, 2015

Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Energy reduction in 3D NoCs through communication optimization.
Computing, 2015

JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Hardware Accelerator Design for Data Centers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Application-Specific Heterogeneous Network-on-Chip Design.
Comput. J., 2014

Voltage island based heterogeneous NoC design through constraint programming.
Computers & Electrical Engineering, 2014

Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

A cache topology-aware multi-query scheduler for multicore architectures.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

AutopaR: An Automatic Parallelization Tool for Recursive Calls.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

Fault-Tolerant Irregular Topology Design Method for Network-on-Chips.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
Hardware/software approaches for reducing the process variation impact on instruction fetches.
ACM Trans. Design Autom. Electr. Syst., 2013

Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems.
IEEE Trans. Computers, 2013

A decoupled local memory allocator.
TACO, 2013

Improving application behavior on heterogeneous manycore systems through kernel mapping.
Parallel Computing, 2013

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design.
J. Electronic Testing, 2013

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

ILP-Based Communication Reduction for Heterogeneous 3D Network-on-Chips.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

2012
Effective Kernel Mapping for OpenCL Applications in Heterogeneous Platforms.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

2011
Multicore Education Through Simulation.
IEEE Trans. Education, 2011

Data locality and parallelism optimization using a constraint-based approach.
J. Parallel Distrib. Comput., 2011

Reducing memory space consumption through dataflow analysis.
Computer Languages, Systems & Structures, 2011

2010
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra.
IET Computers & Digital Techniques, 2010

Improving chip multiprocessor reliability through code replication.
Computers & Electrical Engineering, 2010

Compiler directed network-on-chip reliability enhancement for chip multiprocessors.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Code Scheduling for Optimizing Parallelism and Data Locality.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
Using Data Compression for Increasing Memory System Utilization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Shared scratch pad memory space management across applications.
IJES, 2009

Multicore education through simulation.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Optimizing shared cache behavior of chip multiprocessors.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Optimizing Local Memory Allocation and Assignment through a Decoupled Approach.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

Using dynamic compilation for continuing execution under reduced memory availability.
Proceedings of the Design, Automation and Test in Europe, 2009

Adaptive prefetching for shared cache based chip multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2009

Process variation aware thread mapping for Chip Multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2009

Dynamic thread and data mapping for NoC based CMPs.
Proceedings of the 46th Design Automation Conference, 2009

Slicing based code parallelization for minimizing inter-processor communication.
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Access pattern-based code compression for memory-constrained systems.
ACM Trans. Design Autom. Electr. Syst., 2008

ILP-Based energy minimization techniques for banked memories.
ACM Trans. Design Autom. Electr. Syst., 2008

Software-directed combined cpu/link voltage scaling fornoc-based cmps.
Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

Prefetch throttling and data pinning for improving performance of shared caches.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

SPM management using Markov chain based data access prediction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Profiler and compiler assisted adaptive I/O prefetching for shared storage caches.
Proceedings of the 17th International Conference on Parallel Architecture and Compilation Techniques, 2008

2007
Compiler-Directed Energy Optimization for Parallel Disk Based Systems.
IEEE Trans. Parallel Distrib. Syst., 2007

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
CoRR, 2007

Compiler-Directed Code Restructuring for Operating with Compressed Arrays.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Process Scheduler-Based Approach to NoC Power Management.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An ilp based approach to reducing energy consumption in nocbased CMPS.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Memory bank aware dynamic loop scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Memory-Conscious Code Parallelization Scheme.
Proceedings of the 44th Design Automation Conference, 2007

Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors.
Proceedings of the 44th Design Automation Conference, 2007

Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006
Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Leakage-Aware SPM Management.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Compiler-Directed Management of Leakage Power in Software-Managed Memories.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Shared Scratch-Pad Memory Space Management.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Data Replication in Banked DRAMs for Reducing Energy Consumption.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Minimizing energy consumption of banked memories using data recomputation.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.
Proceedings of the Computer and Information Sciences, 2006

Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

Cache miss clustering for banked memory systems.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An ILP based approach to address code generation for digital signal processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Selective code/data migration for reducing communication energy in embedded MpSoC architectures.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Dynamic partitioning of processing and memory resources in embedded MPSoC architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Dynamic scratch-pad memory management for irregular array access patterns.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Optimizing code parallelization through a constraint network based approach.
Proceedings of the 43rd Design Automation Conference, 2006

Multi-compilation: capturing interactions among concurrently-executing applications.
Proceedings of the Third Conference on Computing Frontiers, 2006

Optimal topology exploration for application-specific 3D architectures.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Compiler-Guided data compression for reducing memory consumption of embedded applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Optimizing Array-Intensive Applications for On-Chip Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 2005

Constraint-based Code mapping for heterogeneous Chip multiprocessors.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Workload Clustering for Increasing Energy Savings on Embedded MPSoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

An Adaptive Locality-Conscious Process Scheduler for Embedded Systems.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

A Data-Driven Approach for Embedded Security.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

An ILP Formulation for Reliability-Oriented High-Level Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Integrating loop and data optimizations for locality within a constraint network based framework.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Using data compression in an MPSoC architecture for improving performance.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Energy management in software-controlled multi-level memory hierarchies.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Integer linear programming based energy optimization for banked DRAMs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems.
Proceedings of the 2005 Design, 2005

BB-GC: Basic-Block Level Garbage Collection.
Proceedings of the 2005 Design, 2005

Nonuniform Banking for Reducing Memory Energy Consumption.
Proceedings of the 2005 Design, 2005

Increasing Register File Immunity to Transient Errors.
Proceedings of the 2005 Design, 2005

Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing.
Proceedings of the 2005 Design, 2005

Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Customized on-chip memories for embedded chip multiprocessors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An ILP-Based Approach to Locality Optimization.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Tuning data replication for improving behavior of MPSoC applications.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Using Data Compression to Increase Energy Savings in Multi-bank Memories.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Data compression for improving SPM behavior.
Proceedings of the 41th Design Automation Conference, 2004

Dynamic on-chip memory management for chip multiprocessors.
Proceedings of the 2004 International Conference on Compilers, 2004


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