Compaction Schemes with Minimum Test Application Time. - Ozgur Sinanoglu; Alex Orailoglu (Asian Test Symposium, 2001)

Space and time compaction schemes for embedded cores. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2001)

RT-level Fault Simulation Based on Symbolic Propagation. - Ozgur Sinanoglu; Alex Orailoglu (VTS, 2001)

Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. - Ozgur Sinanoglu; Alex Orailoglu (DFT, 2002)

Dynamic test data transformations for average and peak power reductions. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (ETW, 2002)

A novel scan architecture for power-efficient, rapid test. - Ozgur Sinanoglu; Alex Orailoglu (ICCAD, 2002)

Scan Power Reduction Through Test Data Transition Frequency Analysis. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (ITC, 2002)

Test Power Reduction through Minimization of Scan Chain Transitions. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (VTS, 2002)

Efficient Construction of Aliasing-Free Compaction Circuitry. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Micro, 2002)

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. - Ozgur Sinanoglu; Alex Orailoglu (Asian Test Symposium, 2003)

Hierarchical Constraint Conscious RT-level Test Generation. - Ozgur Sinanoglu; Alex Orailoglu (DSD, 2003)

Parity-based output compaction for core-based SOCs [logic testing]. - Ozgur Sinanoglu; Alex Orailoglu (ETW, 2003)

Partial Core Encryption for Performance-Efficient Test of SOCs. - Ozgur Sinanoglu; Alex Orailoglu (ICCAD, 2003)

Aggressive Test Power Reduction Through Test Stimuli Transformation. - Ozgur Sinanoglu; Alex Orailoglu (ICCD, 2003)

Modeling Scan Chain Modifications For Scan-in Test Power Minimization. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2003)

Compacting Test Responses for Deeply Embedded SoC Cores. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Des. Test Comput., 2003)

Reducing Average and Peak Test Power Through Scan Chain Modification. - Ozgur Sinanoglu; Ismet Bayraktaroglu; Alex Orailoglu (J. Electron. Test., 2003)

Efficient RT-level fault diagnosis methodology. - Ozgur Sinanoglu; Alex Orailoglu (ASP-DAC, 2004)

Scan Power Minimization through Stimulus and Response Transformations. - Ozgur Sinanoglu; Alex Orailoglu (DATE, 2004)

Pipelined test of SOC cores through test data transformations. - Ozgur Sinanoglu; Alex Orailoglu (ETS, 2004)

Extending the Applicability of Parallel-Serial Scan Designs. - Baris Arslan; Ozgur Sinanoglu; Alex Orailoglu (ICCD, 2004)

Autonomous Yet Deterministic Test of SOC Cores. - Ozgur Sinanoglu; Alex Orailoglu (ITC, 2004)

Fast and energy-frugal deterministic test through efficient compression and compaction techniques. - Ozgur Sinanoglu; Alex Orailoglu (J. Syst. Archit., 2004)

Efficient RT-Level Fault Diagnosis. - Ozgur Sinanoglu; Alex Orailoglu (J. Comput. Sci. Technol., 2005)

Test power reductions through computationally efficient, decoupled scan chain modifications. - Ozgur Sinanoglu; Alex Orailoglu (IEEE Trans. Reliab., 2005)

A non-intrusive isolation approach for soft cores. - Ozgur Sinanoglu; Tsvetomir Petrov (DATE, 2007)

Diagnosis, modeling and tolerance of scan chain hold-time violations. - Ozgur Sinanoglu; Philip Schremmer (DATE, 2007)

Low Cost Scan Test by Test Correlation Utilization. - Ozgur Sinanoglu (J. Comput. Sci. Technol., 2007)

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. - Ozgur Sinanoglu; Erik Jan Marinissen (DATE, 2008)

Peak Power Reduction Through Dynamic Partitioning of Scan Chains. - Sobeeh Almukhaizim; Ozgur Sinanoglu (ITC, 2008)

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors. - Ozgur Sinanoglu (ITC, 2008)

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. - Ozgur Sinanoglu (J. Electron. Test., 2008)

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. - Ozgur Sinanoglu (J. Electron. Test., 2008)

Construction of an adaptive scan network for test time and data volume reduction. - Ozgur Sinanoglu (IET Comput. Digit. Tech., 2008)

Scan Architecture With Align-Encode. - Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Isolation Techniques for Soft Cores. - Ozgur Sinanoglu; Tsvetomir Petrov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments. - Nader Alawadhi; Ozgur Sinanoglu (DFT, 2009)

X-alignment techniques for improving the observability of response compactors. - Ozgur Sinanoglu; Sobeeh Almukhaizim (ITC, 2009)

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. - Ozgur Sinanoglu; Erik Jan Marinissen; Anuja Sehgal; Jeff Fitzgerald; Jeff Rearick (IEEE Des. Test Comput., 2009)

Utilisation of inverse compatibility for test cost reductions. - Ozgur Sinanoglu; Mohammed Al-Mulla; Mohammed Nael Taha (IET Comput. Digit. Tech., 2009)

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks. - Ozgur Sinanoglu; Mohammed Al-Mulla; Noora A. Shunaiber; Alex Orailoglu (J. Comput. Sci. Technol., 2009)

Align-Encode Delay Assignment in the Case of XOR-Decompressors: Impact of Parallel Computations. - Mohammed Al-Mulla; Ozgur Sinanoglu; Mohammed Nael Taha; Nader Alawadhi (J. Interconnect. Networks, 2009)

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. - Sobeeh Almukhaizim; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

X-Align: Improving the Scan Cell Observability of Response Compactors. - Ozgur Sinanoglu; Sobeeh Almukhaizim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Scan Chain Hold-Time Violations: Can They be Tolerated? - Ozgur Sinanoglu; Philip Schremmer (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Pattern Encodability Enhancements for Test Stimulus Decompressors. - Nader Alawadhi; Ozgur Sinanoglu; Mohammed Al-Mulla (Asian Test Symposium, 2010)

XOR-Based Response Compactor Adaptive to X-Density Variation. - Samah Mohamed Saeed; Ozgur Sinanoglu (Asian Test Symposium, 2010)

Add-on blocks and algorithms for improving stimulus compression. - Nader Alawadhi; Ozgur Sinanoglu; Mohammed Al-Mulla (ETS, 2010)

Reconfigurable low-power Concurrent Error Detection in logic circuits. - Sobeeh Almukhaizim; Sara Bunian; Ozgur Sinanoglu (IDT, 2010)

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG. - Junxia Ma; Mohammad Tehranipoor; Ozgur Sinanoglu; Sobeeh Almukhaizim (IDT, 2010)

Predictive analysis for projecting test compression levels. - Ozgur Sinanoglu; Sobeeh Almukhaizim (ITC, 2010)

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power. - Sobeeh Almukhaizim; Shouq Alsubaihi; Ozgur Sinanoglu (J. Electron. Test., 2010)

An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks. - Ozgur Sinanoglu; Mehmet Hakan Karaata; Bader F. AlBdaiwi (IEEE Trans. Computers, 2010)

Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing. - Ozgur Sinanoglu (Asian Test Symposium, 2011)

Toggle-Based Masking Scheme for Clustered Unknown Response Bits. - Ozgur Sinanoglu (ETS, 2011)

Error-resilient design of branch predictors for effective yield improvement. - Sobeeh Almukhaizim; Ozgur Sinanoglu (LATW, 2011)

Revival of partial scan: Test cube analysis driven conversion of flip-flops. - Nader Alawadhi; Ozgur Sinanoglu (VTS, 2011)

Design and analysis of ring oscillator based Design-for-Trust technique. - Jeyavijayan Rajendran; Vinayaka Jyothi; Ozgur Sinanoglu; Ramesh Karri (VTS, 2011)

Expedited response compaction for scan power reduction. - Samah Mohamed Saeed; Ozgur Sinanoglu (VTS, 2011)

Enhancing encoding capacity of combinational test stimulus decompressors. - Nader Alawadhi; Ozgur Sinanoglu; Mohammed Al-Mulla (Sci. China Inf. Sci., 2011)

Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits. - Sobeeh Almukhaizim; Ozgur Sinanoglu (IET Comput. Digit. Tech., 2011)

Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits. - Sobeeh Almukhaizim; Eman AlQuraishi; Ozgur Sinanoglu (J. Low Power Electron., 2011)

Unified 2-D X-Alignment for Improving the Observability of Response Compactors. - Ozgur Sinanoglu; Sobeeh Almukhaizim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Security analysis of logic obfuscation. - Jeyavijayan Rajendran; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (DAC, 2012)

Logic encryption: A fault analysis perspective. - Jeyavijayan Rajendran; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (DATE, 2012)

Toggle-masking scheme for x-filtering. - Abishek Ramdas; Ozgur Sinanoglu (ETS, 2012)

DfT support for launch and capture power reduction in launch-off-capture testing. - Samah Mohamed Saeed; Ozgur Sinanoglu (ETS, 2012)

Adaptive testing of chips with varying distributions of unknown response bits. - Chandra K. H. Suresh; Ozgur Sinanoglu; Sule Ozev (ETS, 2012)

Adaptive testing: Conquering process variations. - Ender Yilmaz; Sule Ozev; Ozgur Sinanoglu; Peter C. Maxwell (ETS, 2012)

Engineering crossbar based emerging memory technologies. - Sachhidh Kannan; Jeyavijayan Rajendran; Ramesh Karri; Ozgur Sinanoglu (ICCD, 2012)

Test access mechanism for chips with spare identical cores. - Ozgur Sinanoglu (IOLTS, 2012)

Retiming scan circuit to eliminate timing penalty. - Ozgur Sinanoglu; Vishwani D. Agrawal (LATW, 2012)

Eliminating Performance Penalty of Scan. - Ozgur Sinanoglu (VLSI Design, 2012)

An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks. - Mehmet Hakan Karaata; Ozgur Sinanoglu; Bader F. AlBdaiwi (Comput. J., 2012)

Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits. - Ozgur Sinanoglu (Comput. J., 2012)

Multi-modal response compaction adaptive to x-density variation. - Samah Mohamed Saeed; Ozgur Sinanoglu (IET Comput. Digit. Tech., 2012)

Security analysis of integrated circuit camouflaging. - Jeyavijayan Rajendran; Michael Sam; Ozgur Sinanoglu; Ramesh Karri (CCS, 2013)

Is split manufacturing secure? - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (DATE, 2013)

Adaptive reduction of the frequency search space for multi-vdd digital circuits. - Chandra K. H. Suresh; Ender Yilmaz; Sule Ozev; Ozgur Sinanoglu (DATE, 2013)

Reconciling the IC test and security dichotomy. - Ozgur Sinanoglu; Naghmeh Karimi; Jeyavijayan Rajendran; Ramesh Karri; Yier Jin; Ke Huang 001; Yiorgos Makris (ETS, 2013)

Sneak path testing and fault modeling for multilevel memristor-based memories. - Sachhidh Kannan; Ramesh Karri; Ozgur Sinanoglu (ICCD, 2013)

Scan attack in presence of mode-reset countermeasure. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (IOLTS, 2013)

High-level synthesis for security and trust. - Jeyavijayan Rajendran; Huan Zhang; Ozgur Sinanoglu; Ramesh Karri (IOLTS, 2013)

VLSI testing based security metric for IC camouflaging. - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (ITC, 2013)

Embedded tutorial: Regaining hardware security and trust. - Ozgur Sinanoglu (LATW, 2013)

New scan-based attack using only the test mode. - Sk Subidh Ali; Ozgur Sinanoglu; Samah Mohamed Saeed; Ramesh Karri (VLSI-SoC, 2013)

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (VLSI-SoC (Selected Papers), 2013)

Sneak-path Testing of Memristor-based Memories. - Sachhidh Kannan; Jeyavijayan Rajendran; Ramesh Karri; Ozgur Sinanoglu (VLSI Design, 2013)

Expedited-compact architecture for average scan power reduction. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Des. Test, 2013)

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints. - Sobeeh Almukhaizim; Sara Bunian; Ozgur Sinanoglu (J. Electron. Test., 2013)

Eliminating the Timing Penalty of Scan. - Ozgur Sinanoglu; Vishwani D. Agrawal (J. Electron. Test., 2013)

Testing Chips With Spare Identical Cores. - Abishek Ramdas; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Scan to Nonscan Conversion via Test Cube Analysis. - Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Predictive Techniques for Projecting Test Data Volume Compression. - Samah Mohamed Saeed; Ozgur Sinanoglu; Sobeeh Almukhaizim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Secure Memristor-based Main Memory. - Sachhidh Kannan; Naghmeh Karimi; Ozgur Sinanoglu (DAC, 2014)

Approximating the age of RF/analog circuits through re-characterization and statistical estimation. - Doohwang Chang; Sule Ozev; Ozgur Sinanoglu; Ramesh Karri (DATE, 2014)

Slack removal for enhanced reliability and trust. - Abishek Ramdas; Samah Mohamed Saeed; Ozgur Sinanoglu (DTIS, 2014)

Test-mode-only scan attack using the boundary scan chain. - Sk Subidh Ali; Ozgur Sinanoglu; Ramesh Karri (ETS, 2014)

New scan attacks against state-of-the-art countermeasures and DFT. - Sk Subidh Ali; Ozgur Sinanoglu; Samah Mohamed Saeed; Ramesh Karri (HOST, 2014)

Test-mode-only scan attack and countermeasure for contemporary scan architectures. - Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu; Ramesh Karri (ITC, 2014)

AES design space exploration new line for scan attack resiliency. - Sk Subidh Ali; Ozgur Sinanoglu; Ramesh Karri (VLSI-SoC, 2014)

Detection, diagnosis, and repair of faults in memristor-based memories. - Sachhidh Kannan; Naghmeh Karimi; Ramesh Karri; Ozgur Sinanoglu (VTS, 2014)

Regaining Trust in VLSI Design: Design-for-Trust Techniques. - Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri (Proc. IEEE, 2014)

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Scan attack on Elliptic Curve Cryptosystem. - Sk Subidh Ali; Ozgur Sinanoglu (DFTS, 2015)

Security analysis of logic encryption against the most effective side-channel attack: DPA. - Muhammad Yasin; Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (DFTS, 2015)

Security implications of cyberphysical digital microfluidic biochips. - Sk Subidh Ali; Mohamed Ibrahim 002; Ozgur Sinanoglu; Krishnendu Chakrabarty; Ramesh Karri (ICCD, 2015)

Transforming between logic locking and IC camouflaging. - Muhammad Yasin; Ozgur Sinanoglu (IDT, 2015)

Power analysis attacks on ARX: An application to Salsa20. - Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (IOLTS, 2015)

A secure design-for-test infrastructure for lifetime security of SoCs. - Jerry Backer; Sk Subidh Ali; Kurt Rosenfeld; David Hély; Ozgur Sinanoglu; Ramesh Karri (ISCAS, 2015)

Timing attack on NEMS relay based design of AES. - Samah Mohamed Saeed; Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (VLSI-SoC, 2015)

TMO: A new class of attack on cipher misusing test infrastructure. - Sk Subidh Ali; Ozgur Sinanoglu (VTS, 2015)

MAGIC: Malicious Aging in Circuits/Cores. - Naghmeh Karimi; Arun Karthik Kanuparthi; Xueyang Wang; Ozgur Sinanoglu; Ramesh Karri (ACM Trans. Archit. Code Optim., 2015)

Fault Analysis-Based Logic Encryption. - Jeyavijayan Rajendran; Huan Zhang; Chi Zhang; Garrett S. Rose; Youngok K. Pino; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Computers, 2015)

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories. - Sachhidh Kannan; Naghmeh Karimi; Ramesh Karri; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures. - Sachhidh Kannan; Naghmeh Karimi; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Guest Editorial Special Section on Hardware Security and Trust. - Ramesh Karri; Farinaz Koushanfar; Ozgur Sinanoglu; Yiorgos Makris; Ken Mai; Ahmad-Reza Sadeghi; Swarup Bhunia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Belling the CAD: Toward Security-Centric Electronic System Design. - Jeyavijayan Rajendran; Aman Ali; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation. - Chandra K. H. Suresh; Sule Ozev; Ozgur Sinanoglu (ACM Trans. Design Autom. Electr. Syst., 2015)

Microfluidic encryption of on-chip biochemical assays. - Sk Subidh Ali; Mohamed Ibrahim 002; Ozgur Sinanoglu; Krishnendu Chakrabarty; Ramesh Karri (BioCAS, 2016)

Activation of logic encrypted chips: Pre-test or post-test? - Muhammad Yasin; Samah Mohamed Saeed; Jeyavijayan Rajendran; Ozgur Sinanoglu (DATE, 2016)

Do you trust your chip? - Ozgur Sinanoglu (DTIS, 2016)

SARLock: SAT attack resistant logic locking. - Muhammad Yasin; Bodhisatwa Mazumdar; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu (HOST, 2016)

CamoPerturb: secure IC camouflaging for minterm protection. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (ICCAD, 2016)

Power-side-channel analysis of carbon nanotube FET based design. - Chandra K. H. Suresh; Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (IOLTS, 2016)

Thwarting timing attacks on NEMS relay based designs. - Bodhisatwa Mazumdar; Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu (VTS, 2016)

Supply-Chain Security of Digital Microfluidic Biochips. - Sk Subidh Ali; Mohamed Ibrahim 002; Jeyavijayan Rajendran; Ozgur Sinanoglu; Krishnendu Chakrabarty (Computer, 2016)

Security Analysis of Anti-SAT. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (IACR Cryptol. ePrint Arch., 2016)

Guest Editorial Special Issue on Secure and Trustworthy Computing. - Ozgur Sinanoglu; Ramesh Karri (ACM J. Emerg. Technol. Comput. Syst., 2016)

A Comparative Security Analysis of Current and Emerging Technologies. - Chandra K. H. Suresh; Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (IEEE Micro, 2016)

On Improving the Security of Logic Locking. - Muhammad Yasin; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Security Assessment of Cyberphysical Digital Microfluidic Biochips. - Sk Subidh Ali; Mohamed Ibrahim 002; Ozgur Sinanoglu; Krishnendu Chakrabarty; Ramesh Karri (IEEE ACM Trans. Comput. Biol. Bioinform., 2016)

A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities. - Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (ACM Trans. Design Autom. Electr. Syst., 2016)

Adapting to Varying Distribution of Unknown Response Bits. - Chandra K. H. Suresh; Ozgur Sinanoglu; Sule Ozev (ACM Trans. Design Autom. Electr. Syst., 2016)

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. - Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Provably-Secure Logic Locking: From Theory To Practice. - Muhammad Yasin; Abhrajit Sengupta; Mohammed Thari Nabeel; Mohammed Ashraf; Jeyavijayan Rajendran; Ozgur Sinanoglu (CCS, 2017)

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. - Johann Knechtel; Ozgur Sinanoglu (DAC, 2017)

What to Lock?: Functional and Parametric Locking. - Muhammad Yasin; Abhrajit Sengupta; Benjamin Carrión Schäfer; Yiorgos Makris; Ozgur Sinanoglu; Jeyavijayan Rajendran (ACM Great Lakes Symposium on VLSI, 2017)

TTLock: Tenacious and traceless logic locking. - Muhammad Yasin; Bodhisatwa Mazumdar; Jeyavijayan (JV) Rajendran; Ozgur Sinanoglu (HOST, 2017)

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. - Abhrajit Sengupta; Satwik Patnaik; Johann Knechtel; Mohammed Ashraf; Siddharth Garg; Ozgur Sinanoglu (ICCAD, 2017)

Evolution of logic locking. - Muhammad Yasin; Ozgur Sinanoglu (VLSI-SoC, 2017)

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Des. Test, 2017)

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. - Johann Knechtel; Ozgur Sinanoglu; Ibrahim Abe M. Elfadel; Jens Lienig; Cliff C. N. Sze (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits Using Variation Sensitive Ring Oscillators. - Chandra K. H. Suresh; Sule Ozev; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases. - Muhammad Yasin; Temesghen Tekeste; Hani H. Saleh; Baker Mohammad; Ozgur Sinanoglu; Mohammed Ismail 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities. - Swarup Bhunia; An Chen; Ozgur Sinanoglu; Jason M. Fung (IEEE Trans. Emerg. Top. Comput., 2017)

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. - Bodhisatwa Mazumdar; Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu (IEEE Trans. Emerg. Top. Comput., 2017)

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. - Muhammad Yasin; Ozgur Sinanoglu; Jeyavijayan Rajendran (IEEE Trans. Inf. Forensics Secur., 2017)

Concerted wire lifting: Enabling secure and cost-effective split manufacturing. - Satwik Patnaik; Johann Knechtel; Mohammed Ashraf; Ozgur Sinanoglu (ASP-DAC, 2018)

Raise your game for split manufacturing: restoring the true functionality through BEOL. - Satwik Patnaik; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu (DAC, 2018)

Advancing hardware security using polymorphic and stochastic spin-hall effect devices. - Satwik Patnaik; Nikhil Rangarajan; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (DATE, 2018)

Towards provably-secure performance locking. - Monir Zaman; Abhrajit Sengupta; Danqing Liu; Ozgur Sinanoglu; Yiorgos Makris; Jeyavijayan (JV) Rajendran (DATE, 2018)

Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (ICCAD, 2018)

Customized locking of IP blocks on a multi-million-gate SoC. - Abhrajit Sengupta; Mohammed Thari Nabeel; Mohammed Ashraf; Ozgur Sinanoglu (ICCAD, 2018)

Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition. - Muhammad Yasin; Ozgur Sinanoglu (ITC, 2018)

ATPG-based cost-effective, secure logic locking. - Abhrajit Sengupta; Mohammed Thari Nabeel; Muhammad Yasin; Ozgur Sinanoglu (VTS, 2018)

Protect Your Chip Design Intellectual Property: An Overview. - Johann Knechtel; Satwik Patnaik; Ozgur Sinanoglu (COINS, 2019)

Attacking Split Manufacturing from a Deep Learning Perspective. - Haocheng Li; Satwik Patnaik; Abhrajit Sengupta; Haoyu Yang; Johann Knechtel; Bei Yu 001; Evangeline F. Y. Young; Ozgur Sinanoglu (DAC, 2019)

MixLock: Securing Mixed-Signal Circuits via Logic Locking. - Julian Leonhard; Muhammad Yasin; Shadi Turk; Mohammed Thari Nabeel; Marie-Minerve Louërat; Roselyne Chotin-Avot; Hassan Aboushady; Ozgur Sinanoglu; Haralampos-G. D. Stratigopoulos (DATE, 2019)

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. - Abhrajit Sengupta; Mohammed Nabeel 001; Johann Knechtel; Ozgur Sinanoglu (DATE, 2019)

Revisiting Logic Locking for Reversible Computing. - Nimisha Limaye; Muhammad Yasin; Ozgur Sinanoglu (ETS, 2019)

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. - Nimisha Limaye; Abhrajit Sengupta; Mohammed Nabeel 001; Ozgur Sinanoglu (ICCAD, 2019)

3D Integration: Another Dimension Toward Hardware Security. - Johann Knechtel; Satwik Patnaik; Ozgur Sinanoglu (IOLTS, 2019)

Logic Locking of Boolean Circuits: Provable Hardware-Based Obfuscation from a Tamper-Proof Memory. - Giovanni Di Crescenzo; Abhrajit Sengupta; Ozgur Sinanoglu; Muhammad Yasin (SECITC, 2019)

Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application. - Julian Leonhard; Marie-Minerve Louërat; Hassan Aboushady; Ozgur Sinanoglu; Haralampos-G. D. Stratigopoulos (SMACD, 2019)

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. - Mohammed Nabeel 001; Mohammed Ashraf; Satwik Patnaik; Vassos Soteriou; Ozgur Sinanoglu; Johann Knechtel (CoRR, 2019)

Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. - Johann Knechtel; Jacek Gosciniak; Alabi Bojesomo; Satwik Patnaik; Ozgur Sinanoglu; Mahmoud Rasras (CoRR, 2019)

Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Des. Test, 2019)

ScanSAT: Unlocking Obfuscated Scan Chains. - Lilas Alrahis; Muhammad Yasin; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2019)

CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist. - Abhrajit Sengupta; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2019)

Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. - Ozgur Sinanoglu; Omer Khan (IEEE Trans. Emerg. Top. Comput., 2019)

Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) - Unlocked. - Fangfei Yang; Ming Tang 002; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2019)

Trustworthy Hardware Design: Combinational Logic Locking Techniques - Muhammad Yasin; Jeyavijayan Rajendran; Ozgur Sinanoglu (Springer, 2020)

DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. - Nimisha Limaye; Ozgur Sinanoglu (DATE, 2020)

Design Obfuscation versus Test. - Farimah Farahmandi; Ozgur Sinanoglu; Ronald D. Blanton; Samuel Pagliarini (ETS, 2020)

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Access, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (CoRR, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor. - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (IEEE Micro, 2020)

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. - Mohammed Nabeel 001; Mohammed Ashraf; Satwik Patnaik; Vassos Soteriou; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Computers, 2020)

Keynote: A Disquisition on Logic Locking. - Abhishek Chakraborty 001; Nithyashankari Gummidipoondi Jayasankaran; Yuntao Liu 001; Jeyavijayan Rajendran; Ozgur Sinanoglu; Ankur Srivastava 001; Yang Xie 001; Muhammad Yasin; Michael Zuzak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. - Satwik Patnaik; Nikhil Rangarajan; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Logic Locking With Provable Security Against Power Analysis Attacks. - Abhrajit Sengupta; Bodhisatwa Mazumdar; Muhammad Yasin; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective. - Abhrajit Sengupta; Mohammed Nabeel 001; Nimisha Limaye; Mohammed Ashraf; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Guest Editors' Introduction: Special Issue on Emerging Technologies in Computer Design. - Ozgur Sinanoglu; Ümit Y. Ogras (IEEE Trans. Emerg. Top. Comput., 2020)

Removal Attacks on Logic Locking and Camouflaging Techniques. - Muhammad Yasin; Bodhisatwa Mazumdar; Ozgur Sinanoglu; Jeyavijayan Rajendran (IEEE Trans. Emerg. Top. Comput., 2020)

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. - Nimisha Limaye; Animesh Basak Chowdhury; Christian Pilato; Mohammed Thari Nabeel; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri (DAC, 2021)

GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. - Lilas Alrahis; Satwik Patnaik; Faiq Khalid; Muhammad Abdullah Hanif; Hani H. Saleh; Muhammad Shafique 001; Ozgur Sinanoglu (DATE, 2021)

Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques. - Nimisha Limaye; Satwik Patnaik; Ozgur Sinanoglu (DATE, 2021)

UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. - Lilas Alrahis; Satwik Patnaik; Muhammad Abdullah Hanif; Muhammad Shafique 001; Ozgur Sinanoglu (ICCAD, 2021)

Security Closure of Physical Layouts ICCAD Special Session Paper. - Johann Knechtel; Jayanth Gopinath; Jitendra Bhandari; Mohammed Ashraf; Hussam Amrouch; Shekhar Borkar; Sung Kyu Lim; Ozgur Sinanoglu; Ramesh Karri (ICCAD, 2021)

Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. - Jens Lienig; Susann Rothe; Matthias Thiele; Nikhil Rangarajan; Mohammed Ashraf; Mohammed Nabeel 001; Hussam Amrouch; Ozgur Sinanoglu; Johann Knechtel (ICCAD, 2021)

Interposer-Based Root of Trust. - Tapojyoti Mandal; Gino Chacon; Johann Knechtel; Ozgur Sinanoglu; Paul Gratz; Vassos Soteriou (CoRR, 2021)

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. - Haocheng Li; Satwik Patnaik; Mohammed Ashraf; Haoyu Yang; Johann Knechtel; Bei Yu 001; Ozgur Sinanoglu; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking. - Nimisha Limaye; Emmanouil Kalligeros; Nikolaos Karousos; Irene G. Karybali; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Breaking CAS-Lock and Its Variants by Exploiting Structural Traces. - Abhrajit Sengupta; Nimisha Limaye; Ozgur Sinanoglu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. - Lilas Alrahis; Muhammad Yasin; Nimisha Limaye; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IEEE Trans. Emerg. Top. Comput., 2021)

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Emerg. Top. Comput., 2021)

Guest Editorial: Special Issue On Emerging Technologies in Computer Design. - Ozgur Sinanoglu; Ümit Y. Ogras (IEEE Trans. Emerg. Top. Comput., 2021)

UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. - Lilas Alrahis; Satwik Patnaik; Johann Knechtel; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2021)

MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. - Lilas Alrahis; Satwik Patnaik; Muhammad Shafique 001; Ozgur Sinanoglu (DATE, 2022)

Embracing Graph Neural Networks for Hardware Security. - Lilas Alrahis; Satwik Patnaik; Muhammad Shafique 001; Ozgur Sinanoglu (ICCAD, 2022)

AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. - Tim Bücher; Lilas Alrahis; Guilherme Paim; Sergio Bampi; Ozgur Sinanoglu; Hussam Amrouch (ICCAD, 2022)

NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. - Mahya Morid Ahmadi; Lilas Alrahis; Alessio Colucci; Ozgur Sinanoglu; Muhammad Shafique 001 (IJCNN, 2022)

Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. - Johann Knechtel; Jayanth Gopinath; Mohammed Ashraf; Jitendra Bhandari; Ozgur Sinanoglu; Ramesh Karri (ISPD, 2022)

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. - Nikhil Rangarajan; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Shubham Rai; Gopal Raut; Heba Abunahla; Baker Mohammad; Santosh Kumar Vishvakarma; Akash Kumar 001; Johann Knechtel; Ozgur Sinanoglu (ISVLSI, 2022)

Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. - Gino A. Chacon; Charles Williams; Johann Knechtel; Ozgur Sinanoglu; Paul V. Gratz (IEEE Comput. Archit. Lett., 2022)

Embracing Graph Neural Networks for Hardware Security (Invited Paper). - Lilas Alrahis; Satwik Patnaik; Muhammad Shafique 001; Ozgur Sinanoglu (CoRR, 2022)

Hide & Seek: Seeking the (Un)-Hidden key in Provably-Secure Logic Locking Techniques. - Satwik Patnaik; Nimisha Limaye; Ozgur Sinanoglu (CoRR, 2022)

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. - Abhrajit Sengupta; Mohammed Nabeel 001; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu (Cryptogr., 2022)

SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. - Nikhil Rangarajan; Johann Knechtel; Dinesh Rajasekharan; Ozgur Sinanoglu (IEEE Embed. Syst. Lett., 2022)

IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism. - Shaza Elsharief; Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2022)

Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. - Johann Knechtel; Tarek Ashraf; Natascha Fernengel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Ozgur Sinanoglu; Hussam Amrouch (Integr., 2022)

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. - Lilas Alrahis; Johann Knechtel; Florian Klemme; Hussam Amrouch; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. - Lilas Alrahis; Abhrajit Sengupta; Johann Knechtel; Satwik Patnaik; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Digitally Assisted Mixed-Signal Circuit Security. - Julian Leonhard; Nimisha Limaye; Shadi Turk; Alhassan Sayed; Alán Rodrigo Díaz Rizo; Hassan Aboushady; Ozgur Sinanoglu; Haralampos-G. Stratigopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. - Satwik Patnaik; Mohammed Ashraf; Haocheng Li; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. - Nikhil Rangarajan; Johann Knechtel; Nimisha Limaye; Ozgur Sinanoglu; Hussam Amrouch (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking. - Lilas Alrahis; Satwik Patnaik; Muhammad Shafique 001; Ozgur Sinanoglu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking. - Lilas Alrahis; Satwik Patnaik; Muhammad Abdullah Hanif; Hani H. Saleh; Muhammad Shafique 001; Ozgur Sinanoglu (IEEE Trans. Emerg. Top. Comput., 2022)

PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans. - Nimisha Limaye; Nikhil Rangarajan; Satwik Patnaik; Ozgur Sinanoglu; Kanad Basu (IEEE Trans. Emerg. Top. Comput., 2022)

AntiDOTE: Protecting Debug Against Outsourced Test Entities. - Nimisha Limaye; Christian Wachsmann; Mohammed Nabeel 001; Mohammed Ashraf; Arun K. Kanuparthi; Ozgur Sinanoglu (IEEE Trans. Emerg. Top. Comput., 2022)

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits. - Shubham Rai; Satwik Patnaik; Ansh Rupani; Johann Knechtel; Ozgur Sinanoglu; Akash Kumar 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ramesh Karri; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Trans. Emerg. Top. Comput., 2022)

Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques. - Nimisha Limaye; Satwik Patnaik; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2022)

Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques. - Satwik Patnaik; Nimisha Limaye; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2022)

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. - Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (ASP-DAC, 2023)

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. - Animesh Basak Chowdhury; Lilas Alrahis; Luca Collini; Johann Knechtel; Ramesh Karri; Siddharth Garg; Ozgur Sinanoglu; Benjamin Tan 001 (DAC, 2023)

AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. - Zeng Wang; Lilas Alrahis; Dominik Sisejkovic; Ozgur Sinanoglu (DSN-S, 2023)

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. - Luca Valente; Asif Veeran; Mattia Sinigaglia; Yvan Tortorella; Alessandro Nadalini; Nils Wistoff; Bruno Sá; Angelo Garofalo; Rafail Psiakis; M. Tolba; Ari Kulmala; Nimisha Limaye; et al. (HCS, 2023)

ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules. - Mahya Morid Ahmadi; Lilas Alrahis; Ozgur Sinanoglu; Muhammad Shafique 001 (IOLTS, 2023)

TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. - Hazem Lashen; Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2023)

FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. - Mahya Morid Ahmadi; Lilas Alrahis; Ozgur Sinanoglu; Muhammad Shafique 001 (ISLPED, 2023)

Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. - Mohammad Eslami; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri; Samuel Pagliarini (ISPD, 2023)

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. - Saideep Sreekumar; Mohammed Ashraf; Mohammed Thari Nabeel; Ozgur Sinanoglu; Johann Knechtel (ISPD, 2023)

Security Closure of IC Layouts Against Hardware Trojans. - Fangzhou Wang; Qijing Wang; Bangqi Fu; Shui Jiang; Xiaopeng Zhang 009; Lilas Alrahis; Ozgur Sinanoglu; Johann Knechtel; Tsung-Yi Ho; Evangeline F. Y. Young (ISPD, 2023)

UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. - Lilas Alrahis; Likhitha Mankali; Satwik Patnaik; Abhrajit Sengupta; Johann Knechtel; Ozgur Sinanoglu (SPACE, 2023)

Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? - Lilas Alrahis; Ozgur Sinanoglu (VTS, 2023)

DNN-Alias: Deep Neural Network Protection Against Side-Channel Attacks via Layer Balancing. - Mahya Morid Ahmadi; Lilas Alrahis; Ozgur Sinanoglu; Muhammad Shafique 001 (CoRR, 2023)

PoisonedGNN: Backdoor Attack on Graph Neural Networks-based Hardware Security Systems. - Lilas Alrahis; Satwik Patnaik; Muhammad Abdullah Hanif; Muhammad Shafique 001; Ozgur Sinanoglu (CoRR, 2023)

FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. - Swetaki Chatterjee; Nikhil Rangarajan; Satwik Patnaik; Dinesh Rajasekharan; Ozgur Sinanoglu; Yogesh Singh Chauhan (IEEE Trans. Emerg. Top. Comput., 2023)

Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. - Likhitha Mankali; Lilas Alrahis; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2023)

RESCUE: Resilient, Scalable, High-Corruption, Compact-Key-Set Locking Framework. - Nimisha Limaye; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. - Dinesh Rajasekharan; Nikhil Rangarajan; Satwik Patnaik; Ozgur Sinanoglu; Yogesh Singh Chauhan (IEEE Trans. Neural Networks Learn. Syst., 2023)

$ tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems. - Lilas Alrahis; Satwik Patnaik; Muhammad Abdullah Hanif; Muhammad Shafique 001; Ozgur Sinanoglu (IEEE Trans. Computers, 2023)

VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques. - Likhitha Mankali; Satwik Patnaik; Nimisha Limaye; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (APCCAS, 2024)

HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition. - Paul R. Genssler; Lilas Alrahis; Ozgur Sinanoglu; Hussam Amrouch (DATE, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (ICCAD, 2024)

Selective Forgetting in Task-Progressive Learning Through Machine Unlearning. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ICMLC, 2024)

Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks. - Mahya Morid Ahmadi; Lilas Alrahis; Ozgur Sinanoglu; Muhammad Shafique 001 (IOLTS, 2024)

Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2024)

Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. - Zhengyao Gu; Diego Troy Lopez; Lilas Alrahis; Ozgur Sinanoglu (ISQED, 2024)

Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ISQED, 2024)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. - Zeng Wang; Lilas Alrahis; Likhitha Mankali; Johann Knechtel; Ozgur Sinanoglu (ISVLSI, 2024)

Locking Decision Tree with State Permutation Obfuscation: Software Implementation. - Rupesh Raj Karn; Ozgur Sinanoglu (NewCAS, 2024)

Benchmarking Backdoor Attacks on Graph Convolution Neural Networks: A Comprehensive Analysis of Poisoning Techniques. - Rupesh Raj Karn; Ozgur Sinanoglu (SPACE, 2024)

INSIGHT: Attacking Industry-Adopted Learning Resilient Logic Locking Techniques Using Explainable Graph Neural Network. - Lakshmi Likhitha Mankali; Ozgur Sinanoglu; Satwik Patnaik (USENIX Security Symposium, 2024)

The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security. - Lilas Alrahis; Mohammed Thari Nabeel; Johann Knechtel; Ozgur Sinanoglu (VLSI-SoC, 2024)

CircuitHD: Brain-Inspired Hyperdimensional Computing for Circuit Recognition. - Paul R. Genssler; Lilas Alrahis; Ozgur Sinanoglu; Hussam Amrouch (IEEE Access, 2024)

Lightweight Masking Against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Thari Nabeel; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (CoRR, 2024)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. - Fangzhou Wang; Qijing Wang; Lilas Alrahis; Bangqi Fu; Shui Jiang; Xiaopeng Zhang 009; Ozgur Sinanoglu; Tsung-Yi Ho; Evangeline F. Y. Young; Johann Knechtel (CoRR, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Mohammed Nabeel 001; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (CoRR, 2024)

NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack. - Prithwish Basu Roy; Johann Knechtel; Akashdeep Saha; Saideep Sreekumar; Likhitha Mankali; Mohammed Thari Nabeel; Debdeep Mukhopadhyay; Ramesh Karri; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2024)

Progressive Learning With Recurrent Neural Network for Sequence Classification. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. - Gino A. Chacon; Charles Williams; Johann Knechtel; Ozgur Sinanoglu; Paul V. Gratz; Vassos Soteriou (ACM Trans. Archit. Code Optim., 2024)

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability. - Tarek Mohamed; Victor M. van Santen; Lilas Alrahis; Ozgur Sinanoglu; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. - Jitendra Bhandari; Likhitha Mankali; Mohammed Nabeel 001; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. - Lakshmi Likhitha Mankali; Jitendra Bhandari; Manaar Alam; Ramesh Karri; Michail Maniatakos; Ozgur Sinanoglu; Johann Knechtel (DATE, 2025)

Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ICISSP (2), 2025)

LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Nabeel 001; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (ISCAS, 2025)

Educational Framework for Power Side-Channel Attacks on Neural Networks in Embedded Systems. - Rupesh Raj Karn; Prithwish Basu Roy; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2025)

GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness. - Akashdeep Saha; Prithwish Basu Roy; Johann Knechtel; Ramesh Karri; Ozgur Sinanoglu; Lilas Alrahis (VTS, 2025)

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. - Johann Knechtel; Mohammad Eslami; Peng Zou; Min Wei; Xingyu Tong 001; Binggang Qiu; Zhijie Cai; Guohao Chen 001; Benchao Zhu; Jiawei Li; Jun Yu 010; Jianli Chen; et al. (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

DEFending Integrated Circuit Layouts. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Inf. Forensics Secur., 2025)

On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning. - Brunno Alves de Abreu; Guilherme Paim; Lilas Alrahis; Paulo F. Flores; Ozgur Sinanoglu; Sergio Bampi; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding. - Zeng Wang; Minghao Shao; Mohammed Nabeel 001; Prithwish Basu Roy; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammed Shafique 001; Johann Knechtel (CoRR, 2025)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination. - Zeng Wang; Minghao Shao; Jitendra Bhandari; Likhitha Mankali; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form. - Prithwish Basu Roy; Akashdeep Saha; Manaar Alam; Johann Knechtel; Michail Maniatakos; Ozgur Sinanoglu; Ramesh Karri (CoRR, 2025)

SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design. - Zeng Wang; Minghao Shao; Rupesh Raj Karn; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

SecureX: Strategically Securing Designs Against Oracle-Less Attacks Using GNN-Based Explainers. - Likhitha Mankali; Ozgur Sinanoglu; Satwik Patnaik (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)