A New Design Technique for Weakly Indicating Function Blocks. - P. Balasubramanian 001; David A. Edwards (DDECS, 2008)

Efficient Realization of Strongly Indicating Function Blocks. - P. Balasubramanian 001; David A. Edwards (ISVLSI, 2008)

Self-timed full adder designs based on hybrid input encoding. - P. Balasubramanian 001; David A. Edwards; Charlie Brej (DDECS, 2009)

Dual-Sum Single-Carry Self-Timed Adder Designs. - P. Balasubramanian 001; Doug A. Edwards (ISVLSI, 2009)

Self-Timed Logic and the Design of Self-Timed Adders. - Padmanabhan Balasubramanian (2010)

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. - P. Balasubramanian 001; David A. Edwards; William B. Toms (VLSI Design, 2012)

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design. - P. Balasubramanian 001; Shigeru Yamashita (PRDC, 2013)

Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. - P. Balasubramanian 001; David A. Edwards; William B. Toms (J. Circuits Syst. Comput., 2013)

A distributed minority and majority voting based redundancy scheme. - P. Balasubramanian 001; Douglas L. Maskell (Microelectron. Reliab., 2015)

ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

Global versus Local Weak-Indication Self-Timed Function Blocks - A Comparative Analysis. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

Power, Delay and Area Comparisons of Majority Voters relevant to TMR Architectures. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. - P. Balasubramanian 001; Shigeru Yamashita (CoRR, 2016)

An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

A Fault Tolerance Improved Majority Voter for TMR System Architectures. - P. Balasubramanian 001; K. Prasad; Nikos E. Mastorakis (CoRR, 2016)

Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder. - P. Balasubramanian 001; K. Prasad (CoRR, 2016)

System Reliability, Fault Tolerance and Design Metrics Tradeoffs in the Distributed Minority and Majority Voting Based Redundancy Scheme. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

FPGA Based Implementation of Distributed Minority and Majority Voting Based Redundancy for Mission and Safety-Critical Applications. - P. Balasubramanian 001; Nikos E. Mastorakis (CoRR, 2016)

Comments on "Dual-rail asynchronous logic multi-level implementation". - P. Balasubramanian 001 (Integr., 2016)

A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking. - P. Balasubramanian 001; Cuong Dang (MWSCAS, 2017)

Approximate quasi-delay-insensitive asynchronous adders: Design and analysis. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell (MWSCAS, 2017)

Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding. - P. Balasubramanian 001; K. Prasad (CoRR, 2017)

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits. - P. Balasubramanian 001; R. T. Naayagi (CoRR, 2017)

Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits. - P. Balasubramanian 001; R. T. Naayagi (CoRR, 2017)

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding. - P. Balasubramanian 001; K. Prasad (CoRR, 2017)

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell; K. Prasad (CoRR, 2017)

Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. - P. Balasubramanian 001; Cuong Dang; Douglas L. Maskell; K. Prasad (CoRR, 2017)

A Critique on "Asynchronous Logic Implementation Based on Factorized DIMS". - P. Balasubramanian 001 (CoRR, 2017)

Indicating Asynchronous Multipliers. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (EECS, 2018)

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (MWSCAS, 2018)

Majority and Minority Voted Redundancy for Safety-Critical Applications. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (MWSCAS, 2018)

A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme. - P. Balasubramanian 001; Douglas L. Maskell; Krishnamachar Prasad (TENCON, 2018)

Hardware Efficient Approximate Adder Design. - P. Balasubramanian 001; Douglas L. Maskell (TENCON, 2018)

A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications. - P. Balasubramanian 001; Douglas L. Maskell (IEEE Access, 2018)

Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking. - P. Balasubramanian 001 (CoRR, 2018)

Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder. - P. Balasubramanian 001 (CoRR, 2018)

Performance Comparison of some Synchronous Adders. - P. Balasubramanian 001 (CoRR, 2018)

Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (EECS, 2019)

Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications. - Jaytrilok Choudhary; P. Balasubramanian 001; Danny M. Varghese; Dhirendra Pratap Singh; Douglas L. Maskell (Comput., 2019)

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. - P. Balasubramanian 001; Douglas L. Maskell; Nikos E. Mastorakis (CoRR, 2019)

Indicating Asynchronous Array Multipliers. - P. Balasubramanian 001; Douglas L. Maskell (CoRR, 2019)

Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders. - P. Balasubramanian 001 (CoRR, 2019)

Hardware Optimized Approximate Adder with Normal Error Distribution. - Raunaq Nayar; Padmanabhan Balasubramanian; Douglas L. Maskell (ISVLSI, 2020)

Quasi-Delay-Insensitive Implementation of Approximate Addition. - Padmanabhan Balasubramanian; Nikos E. Mastorakis (Symmetry, 2020)

An Approximate Adder with Reduced Error and Optimized Design Metrics. - Padmanabhan Balasubramanian; Raunaq Nayar; Douglas L. Maskell (APCCAS, 2021)

A Boolean Heuristic for Disjoint SOP Synthesis. - Padmanabhan Balasubramanian; Anna Bernasconi 001; Valentina Ciriani; Tiziano Villa (DSD, 2021)

Image Compression using Approximate Addition. - Raunaq Nayar; Padmanabhan Balasubramanian; Douglas Leslie Maskell (TENCON, 2021)

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application. - Padmanabhan Balasubramanian; Raunaq Nayar; Douglas L. Maskell; Nikos E. Mastorakis (IEEE Access, 2021)

Gate-Level Static Approximate Adders. - P. Balasubramanian 001; Raunaq Nayar; Douglas L. Maskell (CoRR, 2021)

Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits. - Padmanabhan Balasubramanian; Raunaq Nayar; Okkar Min; Douglas L. Maskell (Comput., 2022)

Fault-Tolerant Design Approach Based on Approximate Computing. - P. Balasubramanian 001; Douglas L. Maskell (CoRR, 2023)

A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency. - Padmanabhan Balasubramanian; Douglas L. Maskell (PACRIM, 2024)

Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic. - Padmanabhan Balasubramanian; Douglas L. Maskell (CoRR, 2024)