Dynamics of fracturing saturated porous media and self-organization of rupture. - Carlo Peruzzo; D. T. Cao; E. Milanese; P. Favia; Francesco Pesavento; F. Hussain; Bernhard A. Schrefler (CoRR, 2019)

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. - Anabela Veloso; Geert Eneman; An De Keersgieter; P. Favia; Andriy Hikavyy; Rongmei Chen; Anne Jourdain; N. Horiguchi (ICICDT, 2022)

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. - Romain Ritzenthaler; Elena Capogreco; E. Dupuy; Hiroaki Arimura; J. P. Bastos; P. Favia; F. Sebaai; D. Radisic; V. T. H. Nguyen; G. Mannaert; B. T. Chan; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2022)

Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. - Souvik Ghosh 001; Quentin Smets; S. Banerjee; Tom Schram; Koen Kennes; R. Verheyen; P. Kumar; M.-E. Boulon; Benjamin Groven; H. M. Silva; Shreya Kundu; Daire Cott; et al. (VLSI Technology and Circuits, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)