Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development. - S. Beckx; M. Demand; S. Locorotondo; K. Henson; M. Claes; V. Paraschiv; D. Shamiryan; P. Jaenen; W. Boullart; S. Degendt (Microelectron. Reliab., 2005)

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. - Yann Civale; Deniz Sabuncuoglu Tezcan; Harold G. G. Philipsen; P. Jaenen; Rahul Agarwal; F. Duval; Philippe Soussan; Youssef Travaly; Eric Beyne (3DIC, 2009)