Efficient false path elimination algorithms for timing verification by event graph preprocessing. - Luc J. M. Claesen; J. P. Schupp; P. Das; P. Johannes; S. Perremans; Hugo De Man (Integr., 1989)

SLOCOP-II: a versatile timing verification system for MOSVLSI. - P. Johannes; P. Das; Luc J. M. Claesen; Hugo De Man (EURO-DAC, 1990)

On the use of hierarchy in timing verification with statically sensitizable paths. - P. Johannes; Luc J. M. Claesen; Hugo De Man (Great Lakes Symposium on VLSI, 1992)

Performance Through Hierarchy in Static Timing Verification. - P. Johannes; Luc J. M. Claesen; Hugo De Man (IFIP Congress (1), 1992)