High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. - Rishan Senanayake; Namitha Liyanage; Sasindu Wijeratne; Sachille Atapattu; Kasun Athukorala; P. M. K. Tharaka; Geethan Karunaratne; R. M. A. U. Senarath; Ishantha Perera; Ashen Ekanayake; Ajith Pasqual (ASAP, 2017)

Runtime rule-reconfigurable high throughput NIPS on FPGA. - P. M. K. Tharaka; D. M. D. Wijerathne; Navoda Perera; Dinushan Vishwajith; Ajith Pasqual (FPT, 2017)