Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits. - P. Pant; Vivek K. De; A. Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. - P. Pant; R. K. Roy; A. Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Innovative practices session 10C: Delay test. - P. Pant; M. Amodeo; Sujal Vora; Jonathon E. Colburn (VTS, 2013)