Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. - Claire Fenouillet-Béranger; P. Perreau; S. Denorme; L. Tosti; François Andrieu; Olivier Weber; S. Barnola; C. Arvet; Y. Campidelli; Sébastien Haendler; R. Beneyton; C. Perrot; et al. (ESSCIRC, 2009)

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. - Olivier Thomas; Jean-Philippe Noel; Claire Fenouillet-Béranger; Marie-Anne Jaud; J. Dura; P. Perreau; Frédéric Boeuf; François Andrieu; D. Delprat; F. Boedt; Konstantin Bourdelle; Bich-Yen Nguyen; et al. (ISCAS, 2010)

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. - Veeresh Deshpande; Sylvain Barraud; Xavier Jehl; Romain Wacquez; Maud Vinet; Remi Coquand; B. Roche; B. Voisin; François Triozon; C. Vizioz; L. Tosti; Bernard Previtali; et al. (ESSDERC, 2012)

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. - François Andrieu; Mikaël Cassé; E. Baylac; P. Perreau; O. Nier; Denis Rideau; R. Berthelon; Franck Pourchon; A. Pofelski; Barbara De Salvo; C. Gallon; Vincent Mazzocchi; et al. (ESSDERC, 2014)

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. - R. Berthelon; François Andrieu; P. Perreau; E. Baylac; A. Pofelski; Emmanuel Josse; Didier Dutartre; A. Claverie; Michel Haond (ESSDERC, 2016)