Improved device variability in scaled MOSFETs with deeply retrograde channel profile. - Jason Woo; Po-Yen Chien; Frank Yang; Seung Chul Song; P. R. Chidi Chidambaram; Joseph Wang 002; Geoffrey Yeap (Microelectron. Reliab., 2014)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. - Jeffrey A. Smith; Kai Ni 004; Ram Krishna Ghosh; Jeff Xu; Mustafa Badaroglu; P. R. Chidi Chidambaram; Suman Datta (ESSDERC, 2017)

Silicon Process Impact on 5G NR mmWave Front End Design and Performance. - Chuan-Cheng Cheng; Jeremy Dunworth; Sriram Kalpat; Haitao Cheng; Gang Liu; Ming-Ta Yang; Wing Sy; Joseph Wang 002; Kamal Sahota; P. R. Chidi Chidambaram (VLSI-DAT, 2019)