A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology. - Varna Puvvada; S. Potla; S. Tamizh Selvam; P. R. Suresh (VLSI Design, 1995)

Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. - N. V. Arvind; P. R. Suresh; V. Sivakumar; Chandrani Pal; Debaprasad Das (VLSI Design, 2001)

Transistor Flaring in Deep Submicron-Design Considerations. - Vipul Singhal; C. B. Keshav; K. G. Surnanth; P. R. Suresh (ASP-DAC/VLSI Design, 2002)

Package-silicon co-design - Experiment with an SOC design. - P. R. Suresh; P. K. Sundararajan; Anshuli Goel; H. Udayakumar; C. Srinivasan; Vasudev Sinari; Raghavendrakumar Ravinutala (VLSI Design, 2004)

Enhancement of total Technical Life of Aero planes. - Balachandran Arumugam; P. R. Suresh; Shriram K. Vasudevan; Kaushik Velusamy (J. Comput. Sci., 2014)

A study of total technical life for an aircraft with implementation and suggestions for improvisation. - Balachandran Arumugam; Shriram K. Vasudevan; P. R. Suresh (Int. J. Adv. Intell. Paradigms, 2020)