Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic. - P. Saravanan 001; P. Chandrasekar; Livya Chandran; Nikilla Sriram; P. Kalpana (VDAT, 2012)

Power analysis attack using neural networks with wavelet transform as pre-processor. - P. Saravanan 001; P. Kalpana; V. Prcethisri; V. Sneha (VDAT, 2014)

Energy Efficient Reversible Building Blocks Resistant to Power Analysis Attacks. - P. Saravanan 001; P. Kalpana (J. Circuits Syst. Comput., 2014)

Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography. - P. Saravanan 001; P. Kalpana (J. Circuits Syst. Comput., 2015)

Low Cost Circuit Level Implementation of PRESENT-80 S-BOX. - Shanthi Rekha Shanmugham; P. Saravanan 001 (VDAT, 2017)

A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine. - P. Saravanan 001; Babu M. Mehtre (VDAT, 2018)

Survey on power analysis attacks and its impact on intelligent sensor networks. - Shanthi Rekha Shanmugham; Saravanan Paramasivam 001 (IET Wirel. Sens. Syst., 2018)

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks. - P. Saravanan 001; P. Kalpana (Wirel. Pers. Commun., 2018)

Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance. - S. Shanthi Rekha; P. Saravanan 001 (VDAT, 2019)

Low-Cost AES-128 Implementation for Edge Devices in IoT Applications. - Shanthi Rekha Shanmugham; P. Saravanan 001 (J. Circuits Syst. Comput., 2019)

Quantum Circuit Design of RECTANGLE Lightweight Cipher. - P. Saravanan 001; J. Jenitha; S. R. Aasish; S. Sanjana (VDAT, 2021)

Hardware Accelerator for Dual Standard Deblocking Filter. - P. Saravanan 001; B. Syndia Priyadarshini; P. Vignesh Kanna; P. Vaishnavi (VLSID, 2021)

Time-shared AES-128 implementation with extremely low-cost for smart card applications. - P. Saravanan 001; Shanthi Rekha Shanmugham (Int. J. Inf. Comput. Secur., 2021)

Authenticated Key Agreement Protocol for Secure Communication Establishment in Vehicle-to-Grid Environment With FPGA Implementation. - Venkatasamy Sureshkumar; P. Chinnaraj; P. Saravanan 001; Ruhul Amin 001; Joel J. P. C. Rodrigues (IEEE Trans. Veh. Technol., 2022)

Compact Quantum Circuit Design of PUFFIN and PRINT Lightweight Ciphers for Quantum Key Recovery Attack. - Saravanan Paramasivam 001; J. Jenitha; S. Sanjana; Majid Haghparast (IEEE Access, 2023)

BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation. - Mohammad Abdussami; Ruhul Amin 001; P. Saravanan 001; Satyanarayana Vollala (Comput. Commun., 2023)

A Hardware Trojan Detection Method for Gate-Level Netlists Employing the CAMELOT Measure. - Priyadharshini Mohanraj; Saravanan Paramasivam 001; Charukesh V.; Nihar Ahamed Fathima A. (ICDCS, 2024)

Three Stage Operational Amplifier with Split Length Differential Input Pair for IoT Applications. - P. Saravanan 001; Harreni V; Krishnaveni V (VDAT, 2024)

DEAC-IoT: Design of lightweight authenticated key agreement protocol for Intra and Inter-IoT device communication using ECC with FPGA implementation. - Mohammad Abdussami; Sanjeev Kumar Dwivedi; Taher Al-Shehari; P. Saravanan 001; Mohammed Kadrie; Taha Alfakih; Hussain Alsalman; Ruhul Amin 001 (Comput. Electr. Eng., 2024)

A Multiobjective Approach for Side-Channel Based Hardware Trojan Detection Using Power Traces. - Priyadharshini Mohanraj; Saravanan Paramasivam 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Low Cost Implementation of Authenticated Encryption Using Spongift. - R. Parthasarathy; P. Saravanan 001 (Wirel. Pers. Commun., 2024)

VAuth: Robust Lightweight Mutual Authentication Protocol Preserving User's Anonymity for VANET With FPGA Implementation. - S. Mugunthan; Venkatasamy Sureshkumar; Saravanan Paramasivam 001; Ruhul Amin 001 (IEEE Trans. Intell. Transp. Syst., 2024)

Side-channel attack resilient implementation of homomorphic encryption using elliptic curve cryptography for secure cloud computing. - Parthasarathy R.; P. Saravanan 001 (Integr., 2025)