Two phase sinusoidal power clocked quasi-static adiabatic logic families. - P. Sasipriya; V. S. Kanchana Bhaaskaran (IC3, 2015)

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL). - P. Sasipriya; V. S. Kanchana Bhaaskaran (J. Circuits Syst. Comput., 2018)

Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power. - P. Sasipriya; Kanchana Bhaaskaran Vettuvanam Somasundaram (J. Low Power Electron., 2018)