Thermal-Aware Non-slicing VLSI Floorplanning Using a Smart Decision-Making PSO-GA Based Hybrid Algorithm. - P. Sivaranjani; A. Senthil Kumar (Circuits Syst. Signal Process., 2015)

Hybrid Particle Swarm Optimization-Firefly algorithm (HPSOFF) for combinatorial optimization of non-slicing VLSI floorplanning. - P. Sivaranjani; A. Senthil Kumar (J. Intell. Fuzzy Syst., 2017)

Verilog Implementation and Functional Verification of Hybrid Cryptography Algorithm. - S. Sasikala; P. Sivaranjani; Balambigai Subramanian; Keerthana M (ICCCNT, 2023)

Design of Arithmetic Logic Unit Using Hybrid Power Reduction Methodologies For Super Computer Applications. - S. Sasikala; Balambigai Subramanian; P. Sivaranjani; V. Udhayasuriyan (ICCCNT, 2023)

Design and Analysis of UART Protocol with Sec-Ded and Implementation on FPGA. - P. Sivaranjani; S. Sasikala; A. Lavanya; M. Keerthana (ICCCNT, 2023)

PSO-DBNet for Peak-to-Average Power Ratio Reduction Using Deep Belief Network. - A. Jameer Basha; M. Ramya Devi; S. Lokesh; P. Sivaranjani; D. Mansoor Hussain; Venkat Padhy (Comput. Syst. Sci. Eng., 2023)

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis. - K. Gavaskar; P. Sivaranjani; S. Elango; G. Nirmal Raja (Wirel. Pers. Commun., 2023)

Two Stage Step-Size Adaptive Filter Design for ECG Denoising. - S. Sasikala; P. Sivaranjani; T. Meeradevi; V. Udhayasuriyan (ICCCNT, 2024)

Review on Logic Styles in CMOS and FinFET Technology. - S. Sasikala; P. Sivaranjani; Kaviya Saravanan; C. Umabharathi (ICCCNT, 2024)

Power Efficient Phase Locked Loop Based FM Demodulation. - P. Sivaranjani; S. Sasikala; M. Supriya (ICCCNT, 2024)

Design and Verification of Low Latency AMBA AXI4 and ACE Protocol for On-Chip Peripheral Communication. - P. Sivaranjani; S. Sasikala; A. Lavanya; M. Keerthana (Wirel. Pers. Commun., 2024)