Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms. - P. Sudhanya; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2021)

Approximate Multipliers Design Using Approximate Adders for Image Processing Applications. - S. P. Joy Vasantha Rani; J. R. Lourdu Jennifer; P. Sudhanya (J. Circuits Syst. Comput., 2022)

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT. - P. Sudhanya; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2025)