Active filter design using cascaded identical low-order (≥ 2) filter sections. - P. V. Ananda Mohan (Proc. IEEE, 1985)

New structures for MOSFET-C filters. - P. V. Ananda Mohan (Proc. IEEE, 1987)

Comments on 'New monolithic switched-capacitor differentiators with good noise rejection'. - P. V. Ananda Mohan (IEEE J. Solid State Circuits, 1992)

Novel oversampled A/D converters based on error spectrum shaping. - Y. V. Ramana Rao; P. V. Ananda Mohan (ISCAS, 1993)

Novel Design for Binary to RNS Converters. - P. V. Ananda Mohan (ISCAS, 1994)

Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. - D. V. Poornaiah; P. V. Ananda Mohan (VLSI Design, 1995)

Capacitor Floatation Scheme using only OTAs and Grounded capacitors. - P. V. Ananda Mohan (J. Circuits Syst. Comput., 1995)

A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. - D. V. Poornaiah; P. V. Ananda Mohan (VLSI Design, 1996)

Efficient Design of Binary to RNS Converters. - P. V. Ananda Mohan (J. Circuits Syst. Comput., 1999)

Fast implementations of Montgomery's modular multiplication algorithm. - P. V. Ananda Mohan (ISCAS (4), 2003)

Floating Capacitance Simulation Using Current Conveyors. - P. V. Ananda Mohan (J. Circuits Syst. Comput., 2005)

Comments on "A 4th-Order Active- Gm-RC Reconfigurable (UMTS/WLAN) Filter". - P. V. Ananda Mohan (IEEE J. Solid State Circuits, 2007)

RNS-To-Binary Converter for a New Three-Moduli Set {2n+1-1, 2n, 2n-1}. - Pemmaraju V. Ananda Mohan (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

RNS-to-Binary Converters for Two Four-Moduli Sets {2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n+1+1}. - Pemmaraju V. Ananda Mohan; A. Benjamin Premkumar (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Implementation of AES S-Boxes using combinational logic. - Rashmi Ramesh Racch; Pemmaraju V. Ananda Mohan (ISCAS, 2008)

Novel First-Order and Second-Order Current-Mode Filters Using Multiple-Output Operational Transconductance Amplifiers. - Dattaguru V. Kamat; P. V. Ananda Mohan; K. Gopalakrishna Prabhu (Circuits Syst. Signal Process., 2010)

Sensitivity Analysis of Third and Fourth-Order Filters. - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2010)

Current-mode operational transconductance amplifier-capacitor biquad filter structures based on Tarmy-Ghausi Active-RC filter and second-order digital all-pass filters. - Dattaguru V. Kamat; Pemmaraju V. Ananda Mohan; K. Gopalakrishna Prabhu (IET Circuits Devices Syst., 2010)

Active-RC filters using two-stage OTAs with and without feed-forward compensation. - Dattaguru V. Kamat; Pemmaraju V. Ananda Mohan; K. Gopalakrishna Prabhu (IET Circuits Devices Syst., 2011)

Comments on "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers". - P. V. Ananda Mohan (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Efficient Implementations for AES Encryption and Decryption. - Rashmi R. Rachh; P. V. Ananda Mohan; Basavaraj S. Anami (Circuits Syst. Signal Process., 2012)

Comments on "Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors". - P. V. Ananda Mohan (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Implementation of AES Key Schedule Using Look-Ahead Technique. - Rashmi R. Rachh; P. V. Ananda Mohan; Basavaraj S. Anami (Circuits Syst. Signal Process., 2014)

Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity". - P. V. Ananda Mohan; Eric A. M. Klumperink; Dlovan H. Mahrof; Bram Nauta (IEEE J. Solid State Circuits, 2014)

Corrections to "A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad". - P. V. Ananda Mohan; Yaohua Zhao; Pui-In Mak; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

RNS to Binary Conversion Using Diagonal Function and Pirlo and Impedovo Monotonic Function. - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2016)

Reverse Conversion Using Core Function, CRT and Mixed Radix Conversion. - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2017)

New Reverse converters for the four-moduli set {2n, 2n-1, 2n+1, 2n-1-1} for n even. - P. S. Phalguna; Dattaguru V. Kamat; P. V. Ananda Mohan (MWSCAS, 2018)

Reverse Converters for the Moduli Set { (2^{n}, 2^{n-1}-1, 2^{n}-1, 2^{n+1}-1 }(n , hbox {Even}) ). - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2018)

RNS-to-Binary Converters for New Three-Moduli Sets {2k-3, 2k-2, 2k-1} and {2k+1, 2k+2, 2k+3}. - P. S. Phalguna; Dattaguru V. Kamat; P. V. Ananda Mohan (J. Circuits Syst. Comput., 2018)

On Actively Compensated Amplifiers Using Negative Impedance Converters. - P. V. Ananda Mohan (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Evaluation of Mixed-Radix Digit Computation Techniques for the Three Moduli RNS {2n-1, 2n, 2n+1-1}. - P. V. Ananda Mohan; P. S. Phalguna (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Public Key Cryptographic Implementation Validation: A Review. - P. V. Ananda Mohan; Abey Jacob; Raghavendra S. Patil (PKIA, 2022)

Hash-based Digital Signatures- A tutorial review. - P. V. Ananda Mohan (PKIA, 2023)

Analysis of GIC-Based Frequency-Dependent Negative Resistance-Based Filters. - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2023)

New Generalized Impedance Converter (GIC)-Based Two-Opamp Active RC Biquads. - P. V. Ananda Mohan (Circuits Syst. Signal Process., 2024)