Low latency and high accuracy archtectures of cordic algorithm for cosine calculation on FPGA. - Gadgil Amruta; Parthe Yogita; Pathak Puja; P. V. Sriniwas Shastry (ICECS, 2008)

Rolled architecture based implementation of AES using T-Box. - P. V. Sriniwas Shastry; Namrata Somani; Amruta Gadre; Bhagyashri Vispute; Mukul S. Sutaone (MWSCAS, 2012)