Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration. - Mohit Upadhyay; Monil Shah; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi (HPCS, 2018)

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement. - P. Veda Bhanu; Pranav Venkatesh Kulkarni; Soumya J.; Linga Reddy Cenkeramaddi; Henning Idsoe (PRIME, 2018)

Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization. - P. Veda Bhanu; Pranav Venkatesh Kulkarni; Sarthak Jain; Soumya J.; Linga Reddy Cenkeramaddi; Henning Idsoe (TENCON, 2018)

A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design. - Mohit Upadhyay; Monil Shah; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi; Henning Idsoe (TENCON, 2018)

A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips. - Monil Shah; Mohit Upadhyay; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi (VDAT, 2018)

Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization. - P. Veda Bhanu; Soumya J. (ICIIS, 2019)

A Link Fault Tolerant Routing Algorithm for Mesh of Tree Based Network-on-Chips. - Joshua Pushparaj; P. Veda Bhanu; Soumya J. (iSES, 2019)

FPGA Implementation of Novel Routing Algorithm for Butterfly-Fat-Tree Topology based NoC Design. - P. Veda Bhanu; S. Jagadheesh; Vasanth Bhat; Garima Agarwal; Soumya J. (PRIME, 2019)

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture. - P. Veda Bhanu; Pranav Venkatesh Kulkarni; Sai Pranavi Avadhanam; Soumya J.; Linga Reddy Cenkeramaddi (VDAT, 2019)

Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture. - Mohit Upadhyay; Monil Shah; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi (VLSID, 2019)

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation. - P. Veda Bhanu; Pranav Venkatesh Kulkarni; Soumya J. (J. Exp. Theor. Artif. Intell., 2019)

Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement. - P. Veda Bhanu; Pranav Venkatesh Kulkarni; Soumya J. (ACM J. Emerg. Technol. Comput. Syst., 2019)

FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design. - P. Veda Bhanu; Chetan Vudadha; Soumya J. (ISCAS, 2020)

Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning. - Jagadheesh Samala; Harshvardhan C. Takawale; Yash Chokhani; P. Veda Bhanu; Soumya J. (VDAT, 2020)

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications. - M. K. Aparna Nair; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi (DSD, 2021)

Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA. - P. Veda Bhanu; Rahul Govindan; Plava Kattamuri; Soumya J.; Linga Reddy Cenkeramaddi (IEEE Access, 2021)

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA. - P. Veda Bhanu; Rahul Govindan; Rajat Kumar; Vishal Singh; Soumya J.; Linga Reddy Cenkeramaddi (IEEE Access, 2021)

Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip. - P. Veda Bhanu; Soumya J. (J. Syst. Archit., 2021)

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation. - Jagadheesh Samala; P. Veda Bhanu; Soumya J.; Linga Reddy Cenkeramaddi (IEEE Access, 2022)

NoC Application Mapping Optimization Using Reinforcement Learning. - Jagadheesh Samala; P. Veda Bhanu; Soumya J. (ACM Trans. Design Autom. Electr. Syst., 2022)