A Software Tool for Simulating Single Event Upsets in a Digital Signal Processor. - Pablo A. Ferreyra; Carlos A. Marqués; Javier P. Gaspar; Ricardo T. Ferreyra (LATW, 2001)

Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied. - Raoul Velazco; A. Corominas; Pablo A. Ferreyra (DFT, 2002)

SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System. - Pablo A. Ferreyra; Carlos A. Marqués; Javier P. Gaspar; Raul Velazco; Ricardo T. Ferreyra (LATW, 2002)

Digital lock in amplifier: study, design and development with a digital signal processor. - Javier P. Gaspar; Suei Feng Chen; Alejandro Gordillo; Mateo Hepp; Pablo A. Ferreyra; Carlos A. Marqués (Microprocess. Microsystems, 2004)

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications. - Ezequiel Brac; Pablo A. Ferreyra; Raoul Velazco; Carlos A. Marqués (LATW, 2009)

Internetworking approaches towards along-track segmented satellite architectures. - Juan A. Fraire; Pablo G. Madoery; Jorge M. Finochietto; Pablo A. Ferreyra; Raoul Velazco (WiSEE, 2016)

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. - M. Solinas; Alexandre Coelho; Juan A. Fraire; Nacer-Eddine Zergainoh; Pablo A. Ferreyra; Raoul Velazco (LATS, 2017)

Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results. - Pablo A. Ferreyra; Juan A. Fraire; Fabian Gomez; Raoul Velazco; Daniel Sánchez 013; Dardo Vinas Viscardi (LATS, 2019)

A Wireless Embedded System for Measuring the Effects of Ionizing Radiations. - Daniel Sánchez 013; Pablo A. Ferreyra; Juan A. Fraire; Fabian Gomez; Raoul Velazco; Dardo Vinas Viscardi (LATS, 2019)

Embedded wireless delay tolerant networks on chips for segmented architectures. - Pablo A. Ferreyra; Rubén Danilo Capkob; Alberto Fabián Gómez; Juan Andres Fraire; Carlos José Barrientos (Int. J. Embed. Syst., 2021)