Rotary router: an efficient architecture for CMP interconnection networks. - Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio; Pablo Prieto (ISCA, 2007)

Reducing the Interconnection Network Cost of Chip Multiprocessors. - Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio (NOCS, 2008)

MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. - Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio (HPCA, 2009)

Improving coherence protocol reactiveness by trading bandwidth for latency. - Lucia G. Menezo; Valentin Puente; Pablo Abad Fidalgo; José-Ángel Gregorio (Conf. Computing Frontiers, 2012)

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. - Pablo Abad Fidalgo; Pablo Prieto; Valentin Puente; José-Ángel Gregorio (ICCD, 2012)

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. - Pablo Abad Fidalgo; Pablo Prieto; Lucia G. Menezo; Adrian Colaso; Valentin Puente; José-Ángel Gregorio (NOCS, 2012)

Balancing Performance and Cost in CMP Interconnection Networks. - Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio (IEEE Trans. Parallel Distributed Syst., 2012)

Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate. - Pablo Abad Fidalgo; Valentin Puente; Lucia G. Menezo; José-Ángel Gregorio (IEEE Trans. Parallel Distributed Syst., 2012)

Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. - Pablo Abad Fidalgo; Pablo Prieto; Lucia G. Menezo; Adrian Colaso; Valentin Puente; José-Ángel Gregorio (DSD, 2013)

LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors. - Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio (ACM Trans. Archit. Code Optim., 2013)

Improving last level shared cache performance through mobile insertion policies (MIP). - Pablo Abad Fidalgo; Pablo Prieto; Valentin Puente; José-Ángel Gregorio (Parallel Comput., 2015)

AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory. - Pablo Abad Fidalgo; Pablo Prieto; Valentin Puente; José-Ángel Gregorio (IEEE Trans. Parallel Distributed Syst., 2016)

Mosaic: A Scalable Coherence Protocol. - Lucia G. Menezo; Valentin Puente; Pablo Abad Fidalgo; José-Ángel Gregorio (Int. J. Parallel Program., 2018)

Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation. - Adrian Colaso; Pablo Prieto; Jose Angel Herrero; Pablo Abad Fidalgo; Lucia G. Menezo; Valentin Puente; José-Ángel Gregorio (IEEE Trans. Parallel Distributed Syst., 2018)

Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. - Adrian Colaso; Pablo Prieto; Pablo Abad Fidalgo; José-Ángel Gregorio; Valentin Puente (IPDPS, 2019)

Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation. - Adrian Colaso; Pablo Prieto; Jose Angel Herrero; Pablo Abad Fidalgo; Valentin Puente; José-Ángel Gregorio (CoRR, 2019)

SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads. - Pablo Prieto; Pablo Abad Fidalgo; Jose Angel Herrero; José-Ángel Gregorio; Valentin Puente (ICPP, 2020)

Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking. - Pablo Prieto; Pablo Abad Fidalgo; José-Ángel Gregorio; Valentin Puente (IEEE Trans. Parallel Distributed Syst., 2021)

Top-Down Performance Profiling on NVIDIA's GPUs. - Alvaro Saiz; Pablo Prieto; Pablo Abad Fidalgo; José-Ángel Gregorio; Valentin Puente (IPDPS, 2022)

Performance Characterization of Popular DNN Models on Out-of-Order CPUs. - Pablo Prieto; Pablo Abad Fidalgo; José-Ángel Gregorio; Valentin Puente (PACT, 2023)