Platform Based on Open-Source Cores for Industrial Applications. - María del Milagro Bolado; Hector Posadas; Javier Castillo; Pablo Huerta; Pablo Sánchez; Carlos Sánchez; Häkan Fouren; Francisco Blasco (DATE, 2004)

A secure self-reconfiguring architecture based on open-source hardware. - Javier Castillo; Pablo Huerta; Víctor López; José Ignacio Martínez (ReConFig, 2005)

A Self-Reconfigurable Multimedia Player on FPGA. - Javier Castillo; Pablo Huerta; César Pedraza; José Ignacio Martínez (ReConFig, 2006)

Secure IP downloading for SRAM FPGAs. - Javier Castillo; Pablo Huerta; José Ignacio Martínez (Microprocess. Microsystems, 2007)

Operating System for Symmetric Multiprocessors on FPGA. - Pablo Huerta; Javier Castillo; Carlos Sánchez; José Ignacio Martínez (ReConFig, 2008)

Self-reconfigurable secure file system for embedded Linux. - César Pedraza; Javier Castillo; José Ignacio Martínez; Pablo Huerta; Carlos S. de La Lama (IET Comput. Digit. Tech., 2008)

Hardware accelerated montecarlo financial simulation over low cost FPGA cluster. - Javier Castillo; José Luis Bosque; Emilio Castillo; Pablo Huerta; José Ignacio Martínez (IPDPS, 2009)

Speeding up combinational synthesis in an FPGA cluster. - César Pedraza; Javier Castillo; José Ignacio Martínez; Pablo Huerta; José Luis Bosque; Javier Cano 001 (PARCO, 2009)

Symmetric Multiprocessor Systems on FPGA. - Pablo Huerta; Javier Castillo; César Pedraza; Javier Cano 001; José Ignacio Martínez (ReConFig, 2009)

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. - Otto Esko; Pekka Jääskeläinen; Pablo Huerta; Carlos S. de La Lama; Jarmo Takala; José Ignacio Martínez (FPL, 2010)

OpenCL-based design methodology for application-specific processors. - Pekka Jääskeläinen; Carlos S. de La Lama; Pablo Huerta; Jarmo Takala (ICSAMOS, 2010)

Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster. - César Pedraza; Emilio Castillo; Javier Castillo; José Luis Bosque; José Ignacio Martínez; Oscar David Robles; Javier Cano 001; Pablo Huerta (J. Syst. Archit., 2010)

A Key Size Configurable High Speed RSA Coprocessor. - Emilio Castillo; Javier Castillo; Javier Cano 001; Pablo Huerta; José Ignacio Martínez (FCCM, 2011)

Parallel pipelined array architectures for real-time histogram computation in consumer devices. - José O. Cadenas; Robert Simon Sherratt; Pablo Huerta; Wen-Chung Kao (IEEE Trans. Consumer Electron., 2011)

Genetic Algorithm for Boolean minimization in an FPGA cluster. - César Pedraza; Javier Castillo; José Ignacio Martínez; Pablo Huerta; José Luis Bosque; Javier Cano 001 (J. Supercomput., 2011)

Parallel pipelined histogram architecture via C-slow retiming. - José O. Cadenas; R. Simon Sherratt; Pablo Huerta; Wen-Chung Kao; Graham M. Megson (ICCE, 2013)

A Parallel Quantum Histogram Architecture. - Graham M. Megson; José O. Cadenas; Robert Simon Sherratt; Pablo Huerta; Wen-Chung Kao (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

C-slow retimed parallel histogram architectures for consumer imaging devices. - José O. Cadenas; Robert Simon Sherratt; Pablo Huerta; Wen-Chung Kao; Graham M. Megson (IEEE Trans. Consumer Electron., 2013)