Performance Assessment of Contents Management in Multilevel On-Chip Caches. - Pablo Ibáñez 001; Víctor Viñals (EUROMICRO, 1996)

Characterization and Improvement of Load/Store Cache-based Prefetching. - Pablo Ibáñez 001; Víctor Viñals; José Luis Briz; María Jesús Garzarán (International Conference on Supercomputing, 1998)

Modeling load address behaviour through recurrences. - Luis M. Ramos; Pablo E. Ibáñez 001; Víctor Viñals; José M. Llabería (ISPASS, 2000)

Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. - María Jesús Garzarán; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (PDP, 2001)

Counteracting Bank Misprediction in Sliced First-Level Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2003)

Contents Management in First-Level Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2004)

Store Buffer Design in First-Level Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ISCA, 2005)

Speeding-Up Synchronizations in DSM Multiprocessors. - Agustín De Dios Hernández; Benjamín Sahelices Fernández; Pablo Ibáñez 001; Víctor Viñals; José M. Llabería (Euro-Par, 2006)

Software Demand, Hardware Supply. - Jesús Alastruey; José Luis Briz; Pablo Ibáñez 001; Víctor Viñals (IEEE Micro, 2006)

Characterization of Apache web server with Specweb2005. - Ana Bosque; Pablo Ibáñez 001; Víctor Viñals; Per Stenström; José María Llabería (MEDEA@PACT, 2007)

Data prefetching in a cache hierarchy with high bandwidth and capacity. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (SIGARCH Comput. Archit. News, 2007)

Low-Cost Adaptive Data Prefetching. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (Euro-Par, 2008)

A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. - Benjamín Sahelices; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (Euro-Par, 2009)

Store Buffer Design for Multibanked Data Caches. - Enrique F. Torres; Pablo Ibáñez 001; Víctor Viñals Yúfera; José María Llabería (IEEE Trans. Computers, 2009)

Filtering Directory Lookups in CMPs with Write-Through Caches. - Ana Bosque; Víctor Viñals; Pablo Ibáñez 001; José María Llabería (Euro-Par (1), 2011)

Multi-level Adaptive Prefetching based on Performance Gradient Tracking. - Luis M. Ramos; José Luis Briz; Pablo E. Ibáñez 001; Víctor Viñals (J. Instr. Level Parallelism, 2011)

Filtering directory lookups in CMPs. - Ana Bosque; Víctor Viñals; Pablo Ibáñez 001; José M. Llabería (Microprocess. Microsystems, 2011)

A review of High Performance Computing foundations for scientists - Pablo García-Risueño; Pablo E. Ibáñez 001 (CoRR, 2012)

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers. - Benjamín Sahelices; Agustín De Dios Hernández; Pablo Ibáñez 001; Víctor Viñals Yúfera; José María Llabería (J. Comput. Sci. Technol., 2012)

ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. - Jorge Albericio; Ruben Gran Tejero; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ACM Trans. Archit. Code Optim., 2012)

The reuse cache: downsizing the shared last-level cache. - Jorge Albericio; Pablo Ibáñez 001; Víctor Viñals; José M. Llabería (MICRO, 2013)

Exploiting reuse locality on inclusive shared last-level caches. - Jorge Albericio; Pablo Ibáñez 001; Víctor Viñals; José María Llabería (ACM Trans. Archit. Code Optim., 2013)

Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints. - Carl Christian Kjelgaard Mikkelsen; Jesús Alastruey-Benedé; Pablo Ibáñez-Marín; Pablo García-Risueño (PPAM (1), 2015)

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. - Alexandra Ferrerón-Labari; Darío Suárez Gracia; Jesús Alastruey-Benedé; Teresa Monreal Arnal; Pablo Ibáñez 001 (IEEE Trans. Computers, 2016)

Reuse Detector: Improving the Management of STT-RAM SLLCs. - Roberto Rodríguez-Rodríguez; Javier Díaz; Fernando Castro; Pablo Ibáñez 001; Daniel Chaver; Víctor Viñals; Juan Carlos Saez; Manuel Prieto-Matías; Luis Piñuel; Teresa Monreal Arnal; José María Llabería (Comput. J., 2018)

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. - Jose Manuel Herruzo; Sonia González-Navarro; Pablo Ibáñez 001; Víctor Viñals; Jesús Alastruey-Benedé; Oscar G. Plata (DCC, 2019)

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero; Luis M. Ramos; Agustín Navarro-Torres; Adolfo Muñoz 001; Joaquín Ezpeleta; José Luis Briz; Ana C. Murillo; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; et al. (WCAE@ISCA, 2019)

ReD: A reuse detector for content selection in exclusive shared last-level caches. - Javier Díaz; Teresa Monreal; Pablo Ibáñez 001; José M. Llabería; Víctor Viñals (J. Parallel Distributed Comput., 2019)

A fault-tolerant last level cache for CMPs operating at ultra-low voltage. - Alexandra Ferrerón-Labari; Jesús Alastruey-Benedé; Darío Suárez Gracia; Teresa Monreal Arnal; Pablo Ibáñez-Marín; Víctor Viñals Yúfera (J. Parallel Distributed Comput., 2019)

Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. - Jose Manuel Herruzo; Sonia González-Navarro; Pablo Ibáñez-Marín; Víctor Viñals Yúfera; Jesús Alastruey-Benedé; Oscar G. Plata (IEEE ACM Trans. Comput. Biol. Bioinform., 2020)

Synchronization Strategies on Many-Core SMT Systems. - Agustín Navarro-Torres; Jesús Alastruey-Benedé; Pablo Ibáñez-Marín; Maria Carpen-Amarie (SBAC-PAD, 2021)

A learning experience toward the understanding of abstraction-level interactions in parallel applications. - Alejandro Valero; Ruben Gran Tejero; Darío Suárez Gracia; Emanuel A. Georgescu; Joaquín Ezpeleta; Pedro Álvarez 001; Adolfo Muñoz 001; Luis M. Ramos; Pablo Ibáñez 001 (J. Parallel Distributed Comput., 2021)

Near-optimal replacement policies for shared caches in multicore processors. - Javier Díaz; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José M. Llabería (J. Supercomput., 2021)

HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. - Carlos Escuin; Asif Ali Khan; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; Jerónimo Castrillón (DroneSE/RAPIDO@HiPEAC, 2022)

Berti: an Accurate Local-Delta Data Prefetcher. - Agustín Navarro-Torres; Biswabandan Panda; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Víctor Viñals Yúfera; Alberto Ros 001 (MICRO, 2022)

Forecasting lifetime and performance of a novel NVM last-level cache with compression. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. - Carlos Escuin; Pablo Ibáñez 001; Teresa Monreal; José M. Llabería; Víctor Viñals (CoRR, 2022)

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. - Rubén Langarita; Adrià Armejach; Javier Setoain; Pablo Ibáñez-Marín; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

RISC-V for Genome Data Analysis: Opportunities and Challenges. - Lorién López-Villellas; Esteve Pineda-Sánchez; Asaf Badouh; Santiago Marco-Sola; Pablo Ibáñez 001; Jesús Alastruey-Benedé; Miquel Moretó (DCIS, 2023)

Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. - Carlos Escuin; Asif Ali Khan; Pablo Ibáñez 001; Teresa Monreal; Jerónimo Castrillón; Víctor Viñals (HPCA, 2023)

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. - Carlos Escuin; Fernando García-Redondo; Mahdi Zahedi; Pablo Ibáñez 001; Teresa Monreal; Víctor Viñals; José María Llabería; James Myers; Julien Ryckaert; Dwaipayan Biswas; Francky Catthoor (ICECS, 2023)

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. - Rubén Langarita; Adrià Armejach; Pablo Ibáñez 001; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2023)

BALANCER: bandwidth allocation and cache partitioning for multicore processors. - Agustín Navarro-Torres; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Víctor Viñals Yúfera (J. Supercomput., 2023)

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code. - Lorién López-Villellas; Carl Christian Kjelgaard Mikkelsen; Juan José Galano-Frutos; Santiago Marco-Sola; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Miquel Moretó; Javier Sancho; Pablo García-Risueño (Comput. Phys. Commun., 2023)

GenArchBench: A genomics benchmark suite for arm HPC processors. - Lorién López-Villellas; Rubén Langarita-Benítez; Asaf Badouh; Víctor Soria Pardos; Quim Aguado-Puig; Guillem López-Paradís; Max Doblas; Javier Setoain; Chulho Kim; Makoto Ono; Adrià Armejach; Santiago Marco-Sola; et al. (Future Gener. Comput. Syst., 2024)

ILVES: Accurate and efficient bond length and angle constraints in molecular dynamics. - Lorién López-Villellas; Carl Christian Kjelgaard Mikkelsen; Juan José Galano-Frutos; Santiago Marco-Sola; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Miquel Moretó; Maria Cristina De Rosa; Pablo García-Risueño (CoRR, 2025)

A Complexity-Effective Local Delta Prefetcher. - Agustín Navarro-Torres; Biswabandan Panda; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Víctor Viñals Yúfera; Alberto Ros 001 (IEEE Trans. Computers, 2025)