Pablo Ibáñez

According to our database1, Pablo Ibáñez authored at least 28 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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PhD thesis 
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Bibliography

2019
A fault-tolerant last level cache for CMPs operating at ultra-low voltage.
J. Parallel Distributed Comput., 2019

ReD: A reuse detector for content selection in exclusive shared last-level caches.
J. Parallel Distributed Comput., 2019


Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.
Proceedings of the Data Compression Conference, 2019

2018
Reuse Detector: Improving the Management of STT-RAM SLLCs.
Comput. J., 2018

2016
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage.
IEEE Trans. Computers, 2016

2015
Accelerating Sparse Arithmetic in the Context of Newton's Method for Small Molecules with Bond Constraints.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

2013
Exploiting reuse locality on inclusive shared last-level caches.
TACO, 2013

The reuse cache: downsizing the shared last-level cache.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache.
TACO, 2012

Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.
J. Comput. Sci. Technol., 2012

A review of High Performance Computing foundations for scientists
CoRR, 2012

2011
Filtering directory lookups in CMPs.
Microprocess. Microsystems, 2011

Multi-level Adaptive Prefetching based on Performance Gradient Tracking.
J. Instruction-Level Parallelism, 2011

Filtering Directory Lookups in CMPs with Write-Through Caches.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2009
Store Buffer Design for Multibanked Data Caches.
IEEE Trans. Computers, 2009

A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
Low-Cost Adaptive Data Prefetching.
Proceedings of the Euro-Par 2008, 2008

2007
Data prefetching in a cache hierarchy with high bandwidth and capacity.
SIGARCH Computer Architecture News, 2007

2006
Software Demand, Hardware Supply.
IEEE Micro, 2006

Speeding-Up Synchronizations in DSM Multiprocessors.
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005
Store Buffer Design in First-Level Multibanked Data Caches.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Contents Management in First-Level Multibanked Data Caches.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Counteracting Bank Misprediction in Sliced First-Level Caches.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2001
Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

2000
Modeling load address behaviour through recurrences.
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1998
Characterization and Improvement of Load/Store Cache-based Prefetching.
Proceedings of the 12th international conference on Supercomputing, 1998

1996
Performance Assessment of Contents Management in Multilevel On-Chip Caches.
Proceedings of the 22rd EUROMICRO Conference '96, 1996


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