FPGA real time synthesis of simplified SIFT algorithm. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (ICDSC, 2018)

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. - Pablo Rubio-Ibáñez; Ramón Ruiz Merino; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; José Ángel Díaz-Madrid; José-Alejandro López Alcantud (Int. J. Circuit Theory Appl., 2018)

Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (ISCAS, 2019)

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions. - Pablo Rubio-Ibáñez; J. Javier Martínez-Álvarez; Ginés Doménech-Asensi (DCIS, 2021)