Exploring Memory Hierarchy with ArchC. - Pablo Viana; Edna Barros; Sandro Rigo; Rodolfo Azevedo; Guido Araujo (SBAC-PAD, 2003)

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. - Pablo Viana; Edna Barros; Sandro Rigo; Rodolfo Azevedo; Guido Araujo (DATE, 2004)

Configurable cache subsetting for fast cache tuning. - Pablo Viana; Ann Gordon-Ross; Eamonn J. Keogh; Edna Barros; Frank Vahid (DAC, 2006)

Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. - Abel Guilhermino Silva-Filho; Pablo Viana; Edna Barros; Manoel Eusébio de Lima (SBAC-PAD, 2006)

A one-shot configurable-cache tuner for improved energy and performance. - Ann Gordon-Ross; Pablo Viana; Frank Vahid; Walid A. Najjar; Edna Barros (DATE, 2007)

Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. - André Silva; Guilherme Álvaro R. M. Esmeraldo; Edna Barros; Pablo Viana (IEEE International Workshop on Rapid System Prototyping, 2007)

A table-based method for single-pass cache optimization. - Pablo Viana; Ann Gordon-Ross; Edna Barros; Frank Vahid (ACM Great Lakes Symposium on VLSI, 2008)

Minimum Effort Design Space Subsetting for Configurable Caches. - Mohamad Hammam Alsafrjalani; Ann Gordon-Ross; Pablo Viana (EUC, 2014)