Performance study of HPC applications on an Arm-based cluster using a generic efficiency model. - Fabio Banchelli; Kilian Peiro; Andrea Querol; Guillem Ramirez-Gargallo; Guillem Ramirez-Miranda; Joan Vinyals; Pablo Vizcaino; Marta Garcia-Gasulla; Filippo Mantovani (PDP, 2020)

Accelerating FFT Using NEC SX-Aurora Vector Engine. - Pablo Vizcaino; Filippo Mantovani; Jesús Labarta (Euro-Par Workshops, 2021)

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V. - Pablo Vizcaino; Georgios Ieronymakis; Nikolaos Dimou; Vassilis Papaefstathiou; Jesús Labarta; Filippo Mantovani (SC Workshops, 2023)

Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study. - Filippo Mantovani; Pablo Vizcaino; Fabio Banchelli; Marta Garcia-Gasulla; Roger Ferrer; Georgios Ieronymakis; Nikolaos Dimou; Vassilis Papaefstathiou; Jesús Labarta (ISC Workshops, 2023)

Acceleration with long vector architectures: Implementation and evaluation of the FFT kernel on NEC SX-Aurora and RISC-V vector extension. - Pablo Vizcaino; Filippo Mantovani; Roger Ferrer; Jesús Labarta (Concurr. Comput. Pract. Exp., 2023)

Graph Computing on Long Vector Architectures (Yes, It Works!). - Pablo Vizcaino; Jesús Labarta; Filippo Mantovani (IPDPS (Workshops), 2024)

QR Factorization on a Long-Vector Processor. - Andrés E. Tomás; Pablo Vizcaino; Enrique S. Quintana-Ortí; Filippo Mantovani (PPAM (2), 2024)

RAVE: RISC-V Analyzer of Vector Executions, A QEMU Tracing Plugin. - Pablo Vizcaino; Filippo Mantovani; Jesús Labarta; Roger Ferrer (PPAM (2), 2024)