RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture. - Padmaja Bhamidipati; Avinash Karanth (ICCD, 2018)

Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. - Subashree Raja; Padmaja Bhamidipati; Xiaobang Liu; Ranga Vemuri (ISVLSI, 2021)

Security Analysis of a System-on-Chip Using Assertion-Based Verification. - Padmaja Bhamidipati; Shanmukha Murali Achyutha; Ranga Vemuri (MWSCAS, 2021)

HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture. - Padmaja Bhamidipati; Avinash Karanth (IEEE Trans. Emerg. Top. Comput., 2022)

ASPIRE: An Intermediate Representation for Abstract Security Policies. - Padmaja Bhamidipati; Ranga Vemuri (VLSID, 2023)

QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips. - Padmaja Bhamidipati; Ranga Vemuri (ISVLSI, 2024)

NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security. - Padmaja Bhamidipati; Ranga Vemuri (MWSCAS, 2024)