Overcoming wireload model uncertainty during physical design. - Padmini Gopalakrishnan; Altan Odabasioglu; Lawrence T. Pileggi; Salil Raje (ISPD, 2001)

An analysis of the wire-load model uncertainty problem. - Padmini Gopalakrishnan; Altan Odabasioglu; Lawrence T. Pileggi; Salil Raje (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Exploring regular fabrics to optimize the performance-cost trade-off. - Lawrence T. Pileggi; Herman Schmit; Andrzej J. Strojwas; Padmini Gopalakrishnan; V. Kheterpal; Aneesh Koorapaty; Chetan Patel; Vyacheslav Rovner; Kim Yaw Tong (DAC, 2003)

A frequency relaxation approach for analog/RF system-level simulation. - Xin Li 001; Yang Xu 017; Peng Li 001; Padmini Gopalakrishnan; Lawrence T. Pileggi (DAC, 2004)

Exploring Logic Block Granularity for Regular Fabrics. - Aneesh Koorapaty; V. Kheterpal; Padmini Gopalakrishnan; M. Fu; Lawrence T. Pileggi (DATE, 2004)

Robust analog/RF circuit design with projection-based posynomial modeling. - Xin Li 001; Padmini Gopalakrishnan; Yang Xu 017; Lawrence T. Pileggi (ICCAD, 2004)

Asymptotic probability extraction for non-normal distributions of circuit performance. - Xin Li 001; Jiayong Le; Padmini Gopalakrishnan; Lawrence T. Pileggi (ICCAD, 2004)

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. - Thomas J. Vogels; Thomas Zanon; Rao Desineni; R. D. (Shawn) Blanton; Wojciech Maly; Jason G. Brown; Jeffrey E. Nelson; Y. Fei; X. Huang; Padmini Gopalakrishnan; Mahim Mishra; Vyacheslav Rovner; et al. (ITC, 2004)

Architecture-aware FPGA placement using metric embedding. - Padmini Gopalakrishnan; Xin Li 001; Lawrence T. Pileggi (DAC, 2006)

Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. - Xin Li 001; Padmini Gopalakrishnan; Yang Xu 017; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Asymptotic Probability Extraction for Nonnormal Performance Distributions. - Xin Li 001; Jiayong Le; Padmini Gopalakrishnan; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only). - Srinivas Siripurapu; Aman Gayasen; Padmini Gopalakrishnan; Nitin Chandrachoodan (FPGA, 2017)

Dissipativity and passivity analysis of Markovian jump impulsive neural networks with time delays. - Gnaneswaran Nagamani; Thirunavukkarasu Radhika; Padmini Gopalakrishnan (Int. J. Comput. Math., 2017)

Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs. - Krishnakumar Nair; Avinash-Chandra Pandey; Siddappa Karabannavar; Meena Arunachalam; John Kalamatianos; Varun Agrawal; Saurabh Gupta 002; Ashish Sirasao; Elliott Delaye; Steven K. Reinhardt; Rajesh Vivekanandham; Ralph Wittig; et al. (IEEE Micro, 2024)