Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. - Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Deepak Kadetotad; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Jae-sun Seo; Yu Cao 001 (BICA, 2014)

Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (BioCAS, 2014)

Architecting 3D vertical resistive memory for next-generation storage systems. - Cong Xu 002; Pai-Yu Chen; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ICCAD, 2014)

Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. - Pai-Yu Chen; Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (DATE, 2015)

Exploiting resistive cross-point array for compact design of physical unclonable function. - Pai-Yu Chen; Runchen Fang; Rui Liu 005; Chaitali Chakrabarti; Yu Cao 001; Shimeng Yu (HOST, 2015)

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. - Pai-Yu Chen; Binbin Lin; I-Ting Wang; Tuo-Hung Hou; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2015)

Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. - Scott Zuloaga; Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2015)

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. - Deepak Kadetotad; Zihan Xu; Abinash Mohanty; Pai-Yu Chen; Binbin Lin; Jieping Ye; Sarma B. K. Vrudhula; Shimeng Yu; Yu Cao 001; Jae-sun Seo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

MNSIM: Simulation platform for memristor-based neuromorphic computing system. - Lixue Xia; Boxun Li; Tianqi Tang 001; Peng Gu; Xiling Yin; Wenqin Huangfu; Pai-Yu Chen; Shimeng Yu; Yu Cao 001; Yu Wang 002; Yuan Xie 001; Huazhong Yang (DATE, 2016)

Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. - Robert Karam; Rui Liu 005; Pai-Yu Chen; Shimeng Yu; Swarup Bhunia (ACM Great Lakes Symposium on VLSI, 2016)

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. - Pai-Yu Chen; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2016)

Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. - Pai-Yu Chen; Shimeng Yu (ISCAS, 2016)

Design of a reliable RRAM-based PUF for compact hardware security primitives. - Ayush Shrivastava; Pai-Yu Chen; Yu Cao 001; Shimeng Yu; Chaitali Chakrabarti (ISCAS, 2016)

Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. - Pai-Yu Chen; Ligang Gao; Shimeng Yu (IEEE Trans. Multi Scale Comput. Syst., 2016)

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. - Pai-Yu Chen; Zhiwei Li 008; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. - Rui Liu 005; Pai-Yu Chen; Shimeng Yu (ISCAS, 2017)

Energy-Efficient Adaptive Computing With Multifunctional Memory. - Wenchao Qian; Pai-Yu Chen; Robert Karam; Ligang Gao; Swarup Bhunia; Shimeng Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. - Manqing Mao; Pai-Yu Chen; Shimeng Yu; Chaitali Chakrabarti (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. - Xiaoyu Sun 001; Xiaochen Peng; Pai-Yu Chen; Rui Liu 005; Jae-sun Seo; Shimeng Yu (ASP-DAC, 2018)

Reliability perspective of resistive synaptic devices on the neuromorphic system performance. - Pai-Yu Chen; Shimeng Yu (IRPS, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. - Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. - Lixue Xia; Boxun Li; Tianqi Tang 001; Peng Gu; Pai-Yu Chen; Shimeng Yu; Yu Cao 001; Yu Wang 002; Yuan Xie 001; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. - Rui Liu 005; Pai-Yu Chen; Xiaochen Peng; Shimeng Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures. - Pai-Yu Chen; Shimeng Yu (IEEE Des. Test, 2019)