A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. - Po-Yao Chuang; Pai-Yu Tan; Cheng-Wen Wu; Juin-Ming Lu (DAC, 2020)

A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. - Pai-Yu Tan; Po-Yao Chuang; Yen-Ting Lin; Cheng-Wen Wu; Juin-Ming Lu (CoRR, 2020)

An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. - Pai-Yu Tan; Cheng-Wen Wu; Juin-Ming Lu (DATE, 2021)

A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. - Ya-Chi Cheng; Pai-Yu Tan; Cheng-Wen Wu; Ming-Der Shieh; Chien-Hui Chuang; Gordon Liao (ITC-Asia, 2022)

Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. - Shian-Yu Lin; Pai-Yu Tan; Cheng-Wen Wu; Ming-Der Shieh; Chien-Hui Chuang; Gordon Liao (ITC-Asia, 2022)

Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. - Ya-Chi Cheng; Pai-Yu Tan; Cheng-Wen Wu; Ming-Der Shieh; Chien-Hui Chuang; Gordon Liao (ITC, 2022)

A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. - Pai-Yu Tan; Chih-Hsuan Tung; Cheng-Wen Wu; Mincent Lee; Gordon Liao (VLSI-DAT, 2022)

A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. - Pai-Yu Tan; Cheng-Wen Wu (ASP-DAC, 2023)

A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation. - Pai-Yu Tan; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2023)