Bounds on signal delay in RC mesh networks. - Pak K. Chan; Martine D. F. Schlag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Algorithms for Library-Specific Sizing of Combinational Logic. - Pak K. Chan (DAC, 1990)

Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. - Pak K. Chan; Martine D. F. Schlag (IEEE Trans. Computers, 1990)

Computing signal delay in general RC networks by tree/link partitioning. - Pak K. Chan; Kevin Karplus (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Delay optimization of carry-skip adders and block carry-lookahead adders. - Pak K. Chan; Martine D. F. Schlag; Clark D. Thomborson; Vojin G. Oklobdzija (IEEE Symposium on Computer Arithmetic, 1991)

Comments on 'Asymptotic waveform evaluation for timing analysis'. - Pak K. Chan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. - Martine D. F. Schlag; Jackson Kong; Pak K. Chan (ICCD, 1992)

Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. - Pak K. Chan; Martine D. F. Schlag; Clark D. Thomborson; Vojin G. Oklobdzija (IEEE Trans. Computers, 1992)

On Routability Prediction for Field-Programmable Gate Arrays. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (DAC, 1993)

Spectral K-Way Ratio-Cut Partitioning and Clustering. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (DAC, 1993)

Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. - Martine D. F. Schlag; Pak K. Chan; Jackson Kong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Spectral K-way ratio-cut partitioning and clustering. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Routability-driven technology mapping for lookup table-based FPGA's. - Martine D. F. Schlag; Jackson Kong; Pak K. Chan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Spectral-Based Multi-Way FPGA Partitioning. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (FPGA, 1995)

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. - Jason Y. Zien; Martine D. F. Schlag; Pak K. Chan (ICCAD, 1996)

Spectral-based multiway FPGA partitioning. - Pak K. Chan; Martine D. F. Schlag; Jason Y. Zien (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Acceleration of an FPGA router. - Pak K. Chan; Martine D. F. Schlag (FCCM, 1997)

Hybrid spectral/iterative partitioning. - Jason Y. Zien; Pak K. Chan; Martine D. F. Schlag (ICCAD, 1997)

Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. - Pak K. Chan; Mark J. Boyd; Sezer Gören 001; K. Klenk; V. Kodavati; R. Kundu; M. Margolese; J. Sun; Katsuharu Suzuki; E. Thorne; X. Wang; J. Xu; et al. (FCCM, 1999)

Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. - Jason Y. Zien; Martine D. F. Schlag; Pak K. Chan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

New parallelization and convergence results for NC: a negotiation-based FPGA router. - Pak K. Chan; Martine D. F. Schlag (FPGA, 2000)

A low-offset class-AB CMOS operational amplifier. - Pak K. Chan; Liter Siek; Hwee C. Tay; Jing H. Su (ISCAS, 2000)

Distributed-memory parallel routing for field-programmable gatearrays. - Pak K. Chan; Martine D. F. Schlag; Carl Ebeling; Larry McMurchie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Parallel placement for field-programmable gate arrays. - Pak K. Chan; Martine D. F. Schlag (FPGA, 2003)