Asynchronous Design Methodology for an Efficient Implementation of Low power ALU. - Palanichamy Manikandan; B. D. Liu; L. Y. Chiou; G. Sundar; Chittaranjan R. Mandal (APCCAS, 2006)

Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (ACM Great Lakes Symposium on VLSI, 2009)

Path-Delay Fault Testing in Embedded Content Addressable Memories. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (DSD, 2010)

Experiments with ABIST test methodology applied to path delay fault testing. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (EWDTS, 2010)

An Enhanced Path Delay Fault Simulator for Combinational Circuits. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (DSD, 2011)

A programmable BIST with macro and micro codes for embedded SRAMs. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas; Mohammad Areef (EWDTS, 2011)

Design of embedded TCAM based longest prefix match search engine. - Palanichamy Manikandan; Bjørn B. Larsen; Einar J. Aas (Microprocess. Microsystems, 2011)

Quantum modeling and repairing digital systems. - Baghdadi Ammar Awni Abbas; Vladimir Ivanovich Hahanov; Palanichamy Manikandan; Eugenia Litvinova; S. Dementiev (EWDTS, 2013)

Path Delay Fault Test and BIST. - Palanichamy Manikandan (2013)

Hardware Trojan prevention using layout-level design approach. - Papa-Sidi Ba; Palanichamy Manikandan; Sophie Dupuis; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ECCTD, 2015)

Selective Algorithms for Built-In Self-Test and Self-Diagnosis in Embedded SRAMS. - Palanichamy Manikandan; Mohammad Areef; Bjørn B. Larsen; Vladimir Hahanov (J. Low Power Electron., 2015)

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. - Papa-Sidi Ba; Sophie Dupuis; Palanichamy Manikandan; Marie-Lise Flottes; Giorgio Di Natale; Bruno Rouzeyre (ISVLSI, 2016)

Revolutionizing Industrial IoT with LoRaWAN for Smarter and Greener Industries. - Palanichamy Manikandan; Ramesh Patel; Sundar Gopalakrishnan; Karthikeyan Palaniswamy (EWDTS, 2024)

Advanced Path Delay Fault Testing Strategies in High-Performance Digital Circuits. - Palanichamy Manikandan; Ramesh Patel; Sundar Gopalakrishnan; Karthikeyan Palaniswamy (EWDTS, 2024)